SAN JOSE, CA–(Marketwired – November 13, 2013) – Cadence Design Systems, Inc. (NASDAQ: CDNS) — If you want to get on the fast track to design signoff, don’t miss Cadence’s Signoff Summit — a day-long event that will help you shave weeks off design closure.
WHEN:
Thursday, November 21, 2013
WHERE:
Cadence Design Systems
Building 10 Auditorium
2655 Seely Ave,
San Jose, CA 95134
MORE ABOUT THE SUMMIT:
The summit will include keynote addresses plus sessions covering the multiple solution components that comprise a comprehensive signoff solution:
- Power analysis and signoff
- Parasitic extraction
- Digital timing closure and signoff
- Physical verification
- Design for manufacturing (DFM)
There will be extended focus on the new Cadence® timing and power signoff solutions, including the Tempus™ Timing Signoff Solution and Voltus™ IC Power Integrity Solution. The Tempus Timing Signoff Solution, announced in May 2013, generated huge attention at DAC. Announced this week, the Voltus IC Power Integrity Solution raises the bar for power analysis and signoff.
For the full agenda, please click here.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
