SAN JOSE, Calif — Sep 17, 2013 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today additional details about its series of RTL signoff seminars being held in Beijing, Shanghai, Hsinchu and Seoul.

The day-long seminars present details of all the technologies required to implement a true RTL signoff flow. Clock Domain Crossing (CDC) analysis, verification completeness, power analysis, timing constraint checking, testability analysis and programmed RTL restructuring are all presented in detail, with practical examples of how these technologies are used to implement reliable IP and SoC level RTL signoff flows.

Executive staff from Atrenta’s Asia Pacific team will be present, as well as local technical experts and product marketing owners from Atrenta’s corporate headquarters in San Jose, CA. Customer testimonials are also planned.

To find out more details about dates and locations and to sign up for one of these free seminars, visit http://www.atrenta.com/AsiaSeminars2013/.

About Atrenta

Atrenta’s SpyGlass Predictive Analyzer^® significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScope™ verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.                   

SpyGlass from Atrenta: Insight. Efficiency. Confidence.   www.atrenta.com