industry news
Subscribe Now

Mentor Graphics Questa Verification Platform Adds Software-Driven Verification for Multi-Core SoC Designs

WILSONVILLE, Ore., July 15, 2013—Mentor Graphics Corp. (NASDAQ: MENT) today announced that intelligent software-driven verification (iSDV) has been added to the Questa® functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. As a result, engineering teams find more system level design bugs earlier in the verification process—during simulation or emulation, when they are easier and more cost effective to debug—before they escape into the prototype lab.

“To fully verify our high performance SoC bus fabric subsystems, we have to generate all kinds of complex traffic scenarios. Using Questa’s intelligent testbench automation we are able to achieve all of our performance and functional verification goals while shaving time off our schedule,” said Galen Blake, Altera senior verification architect. “With Questa iSDV we can run embedded C test programs with RTL level testbenches allowing us to fully verify our system under stressful, but realistic, operational conditions, giving us the highest degree of confidence.”

The Questa iSDV technology addresses a common challenge encountered by many engineering teams verifying multi-core SoC designs. As processors, memory, interconnect and peripherals are assembled, creating system level test programs is complex and time-consuming. Manually writing directed tests in C is not scalable, and constrained random testing in C is not practical. As a result, most verification teams jump straight to hardware/software co-verification or worse yet, to the prototype lab, missing a critical phase of verification.

“Writing embedded test programs manually is difficult, but jumping from a handful of tests straight to booting an OS, loading drivers and running software applications is like going from the desert to drinking from a fire hose,” said Mark Olen, verification solutions technologist, Mentor. “Questa iSDV bridges the gap between IP block and full system level verification by successfully applying intelligent testbench automation at the system level.”

While writing directed tests in C to verify single-core designs at the system level is challenging, today’s multi-core, multi-threaded designs have made this process virtually impossible. Questa iSDV automates this process, creating embedded test programs that run in either the Questa verification or Veloce® emulation environments offering scalability across engines.

Product Availability

The Questa iSDV tool is available immediately as part of the Questa functional verification platform. For product information, contact your Mentor Graphics sales representative, call 800-547-3000 or visit the website at http://www.mentor.com/products/fv/.

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of about $1,090 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site:http://www.mentor.com/.

Leave a Reply

featured blogs
Mar 24, 2023
With CadenceCONNECT CFD less than a month away, now is the time to make your travel plans to join us at the Santa Clara Convention Center on 19 April for our biggest CFD event of the year. As a bonus, CadenceCONNECT CFD is co-located with the first day of CadenceLIVE Silicon ...
Mar 23, 2023
Explore AI chip architecture and learn how AI's requirements and applications shape AI optimized hardware design across processors, memory chips, and more. The post Why AI Requires a New Chip Architecture appeared first on New Horizons for Chip Design....
Mar 10, 2023
A proven guide to enable project managers to successfully take over ongoing projects and get the work done!...

featured video

First CXL 2.0 IP Interoperability Demo with Compliance Tests

Sponsored by Synopsys

In this video, Sr. R&D Engineer Rehan Iqbal, will guide you through Synopsys CXL IP passing compliance tests and demonstrating our seamless interoperability with Teladyne LeCroy Z516 Exerciser. This first-of-its-kind interoperability demo is a testament to Synopsys' commitment to delivering reliable IP solutions.

Learn more about Synopsys CXL here

featured chalk talk

Enable Sustainable Enterprises of the Future
Did you know that buildings are responsible for 40% of global energy consumption and 33% of greenhouse gas emissions? One way we can help both modernize and increase sustainability in our buildings is by adding 10BASE-T1L to our building controllers. In this episode of Chalk Talk, Amelia Dalton chats with Salem Gharbi from Analog Devices about how we can enable sustainable enterprises with ethernet connected building controllers. They examine the10BASE-T1L flexible design solutions that Analog Devices offers, how exiting?building infrastructure can take advantage of 10BASE-T1L and how you can get started on your next sustainable enterprise journey.
Dec 20, 2022
12,957 views