industry news
Subscribe Now

Mentor Graphics Questa Verification Platform Adds Software-Driven Verification for Multi-Core SoC Designs

WILSONVILLE, Ore., July 15, 2013—Mentor Graphics Corp. (NASDAQ: MENT) today announced that intelligent software-driven verification (iSDV) has been added to the Questa® functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. As a result, engineering teams find more system level design bugs earlier in the verification process—during simulation or emulation, when they are easier and more cost effective to debug—before they escape into the prototype lab.

“To fully verify our high performance SoC bus fabric subsystems, we have to generate all kinds of complex traffic scenarios. Using Questa’s intelligent testbench automation we are able to achieve all of our performance and functional verification goals while shaving time off our schedule,” said Galen Blake, Altera senior verification architect. “With Questa iSDV we can run embedded C test programs with RTL level testbenches allowing us to fully verify our system under stressful, but realistic, operational conditions, giving us the highest degree of confidence.”

The Questa iSDV technology addresses a common challenge encountered by many engineering teams verifying multi-core SoC designs. As processors, memory, interconnect and peripherals are assembled, creating system level test programs is complex and time-consuming. Manually writing directed tests in C is not scalable, and constrained random testing in C is not practical. As a result, most verification teams jump straight to hardware/software co-verification or worse yet, to the prototype lab, missing a critical phase of verification.

“Writing embedded test programs manually is difficult, but jumping from a handful of tests straight to booting an OS, loading drivers and running software applications is like going from the desert to drinking from a fire hose,” said Mark Olen, verification solutions technologist, Mentor. “Questa iSDV bridges the gap between IP block and full system level verification by successfully applying intelligent testbench automation at the system level.”

While writing directed tests in C to verify single-core designs at the system level is challenging, today’s multi-core, multi-threaded designs have made this process virtually impossible. Questa iSDV automates this process, creating embedded test programs that run in either the Questa verification or Veloce® emulation environments offering scalability across engines.

Product Availability

The Questa iSDV tool is available immediately as part of the Questa functional verification platform. For product information, contact your Mentor Graphics sales representative, call 800-547-3000 or visit the website at http://www.mentor.com/products/fv/.

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of about $1,090 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site:http://www.mentor.com/.

Leave a Reply

featured blogs
Apr 19, 2024
In today's rapidly evolving digital landscape, staying at the cutting edge is crucial to success. For MaxLinear, bridging the gap between firmware and hardware development has been pivotal. All of the company's products solve critical communication and high-frequency analysis...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Power High-Performance Applications with Renesas RA8 Series MCUs
Sponsored by Mouser Electronics and Renesas
In this episode of Chalk Talk, Amelia Dalton and Kavita Char from Renesas explore the first 32-bit MCUs based on the new Arm® Cortex® -M85 core. They investigate how these new MCUs bridge the gap between MCUs and MPUs, the advanced security features included in this new MCU portfolio, and how you can get started using the Renesas high performance RA8 series in your next design. 
Jan 9, 2024
14,667 views