SAN JOSE, CALIF. — May 14, 2013 — Forte Design Systems™, the #1 provider of software to enable design at a higher level of abstraction, today unwrapped its enhanced Cynthesizer™ SystemC-based high-level synthesis (HLS) product.
The new version includes low power synthesis capabilities, core synthesis algorithms, and a new SystemC integrated development environment (IDE).
“Power efficiency is necessary across the spectrum of devices, and is becoming increasingly more important as the explosion of mobile devices drives the need for big data and cloud devices,” says long-time Cynthesizer user Steven Frank, Panève chief executive officer (CEO). “Panève leverages Cynthesizer’s unique capabilities to develop radically new big-data architectures that are inherently more efficient in both power and performance. To be able to further optimize power efficiency of a synthesized SystemC design automatically and with minimal engineering effort further validates the SystemC design path and Cynthesizer.”
Next-Generation Synthesis Core
“Cynthesizer 5 defines the next generation of high-level synthesis technologies,” remarks Brett Cline, Forte’s vice president of marketing and sales. “We’ve leveraged more than a decade of production design experience to allow design teams to get to better results more quickly. Cynthesizer continues to lead the way for quality of results and now includes several advanced optimizations for low power design.”
Cynthesizer 5 includes Forte’s new “C5” synthesis core, introducing a new architecture that combines the scheduling and allocation phases of the tool, improving predictability and quality of results. New scheduling algorithms allow Cynthesizer to quickly test multiple design microarchitectures and schedules to find the best possible area, performance, and power based on the designers constraints. For existing users, the new C5 core improves area results 9% on average compared to previous Cynthesizer releases.
Low Power Design
Managing power usage is one of the biggest challenges for design engineers. With Cynthesizer 5, design teams can automate complex low power optimizations often difficult or impossible to realize with hand-written register transfer level (RTL) code. Designers can use Cynthesizer’s design exploration capabilities to trade off area, performance, and power for a given set of design constraints.
Cynthesizer 5 introduces three major new user-controlled power optimizations to minimize datapath power, register power, clock tree power, and memory power. The patent pending HLS-optimized clock gating technology analyzes and optimizes the design microarchitecture to find additional clock gating opportunities often impossible to find with RTL-based power optimizers. The patent-pending finite state machine (FSM) optimization minimizes power in the FSM as well as power consumed by false switching in the datapath. Finally, memory power optimizations allow designers to optimize memory accesses for performance or power. The combination of these new optimizations can yield power reductions of 60% or more depending on the design.
The new power optimization features complement the existing Cynthesizer low power features. They include quarter- and half-speed memory architectures, low power memory modes, clock domain crossing circuitry for designs with multiple clock speeds, RTL coding techniques optimized for downstream RTL tools, and integrations with popular RTL power analysis and optimizations products.
SystemC IDE and Analysis Environment
The Cynthesizer Workbench graphical user interface included with Cynthesizer 5 includes a SystemC Integrated Development Environment (IDE), making SystemC development easy and intuitive for new users and advanced users alike. Beyond typical IDE features, the Cynthesizer Workbench also provides several SystemC design “kick-starters” to quickly create new models using pre-defined templates to reduce design and debug time.
The internals of the Cynthesizer Workbench have also been redesigned to allow faster design, debug, and analysis of SystemC models and the resulting RTL designs. The analysis environment includes SystemC and RTL source linking, waveforms, and other tools to optimize design results.
Forte will demonstrate its entire Cynthesizer and CellMath™ product portfolio at the 50th Design Automation Conference (DAC) in Booth #1547 Monday, June 3, through Wednesday, June 5, from 9 a.m. until 6 p.m. daily at the Austin Convention Center in Austin, Texas. Private sessions can be requested at:www.ForteDS.com/DAC2013. The DAC website can be found at: www.dac.com.
Cynthesizer 5 will be available in Q2’13. Pricing is available upon request.
About Forte Design Systems
Forte Design Systems™ is the #1 provider of electronic system-level (ESL) synthesis software, confirmed by Gary Smith EDA, provider of market intelligence for the global Electronic Design Automation (EDA) market. Forte’s software enables design at a higher level of abstraction and improves design results. Its innovative synthesis technologies and intellectual property offerings allow design teams creating complex electronic chips and systems to reduce their overall design and verification time. More than half of the top 20 worldwide semiconductor companies use Forte’s products in production today for ASIC, SoC and FPGA design. Forte is headquartered in San Jose, Calif., with additional offices in England, France, Japan, Korea and the United States. For more information, visit www.ForteDS.com.