MOUNTAIN VIEW, Calif., March 25, 2013 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the immediate availability of its PrimeTime® ADV solution, a new configuration of its market-leading PrimeTime static timing analysis and signoff product. PrimeTime ADV includes advanced leakage recovery and will incorporate physical-aware signoff-driven engineering change order (ECO) guidance technology, which work in conjunction with the latest innovations for Synopsys’ IC Compiler™ solution to enable the fastest path to timing closure and the lowest leakage power for gigahertz IC design implementation.
Advanced designs using deep submicron process technology, especially those using FD-SOI and 3-D structures, are undergoing an evolution as Moore’s law drives device integration, challenging performance and power scalability to keep pace. Chips are packing more and more functionality, leading to high cell utilization complicated by stringent power and margin requirements. These challenges stress the timing closure cycle, leading to more ECO iterations.
“Strong ECO support with tight links between signoff timing and place and route technologies has emerged as a key requirement for our next-generation 28 nm FDSOI designs to achieve timing closure on schedule,” said Indavong Vongsavady, director, Central CAD & Design Solutions at STMicroelectronics Technology R&D. “PrimeTime ECO’s scalability, with its lightweight infrastructure and its aggressive leakage recovery algorithms, tightly coupled with IC Compiler’s versatility to implement the ECO guidance, is the optimal approach for advanced timing closure.”
Built on patented PrimeTime ECO technology, the new leakage and physical-aware ECO enhancements are easy to integrate into the existing flow, enabling the fastest ECO cycle in the least number of iterations. With knowledge of the physical environment gained in PrimeTime, improved ECO choices can be made and physical-aware ECO guidance will be provided to the place and route tool. IC Compiler uses enhanced guidance to make more informed placement and routing decisions, and to minimize the physical impact of the ECO, which results in less iterations. Complementing IC Compiler’s low power and leakage optimization capabilities, PrimeTime ADV extends leakage recovery to signoff analysis, enabling lower power consumption while preserving signoff timing across multiple mode and process corner scenarios.
“Increasing design functionality, timing and power closure, and rigid tapeout schedules are key challenges for signoff at new process geometries,” said Jacob Avidan, vice president of engineering for static timing products at Synopsys. “PrimeTime ADV provides a leap forward in designer productivity, enabling the lowest leakage power and highest frequency designs to meet today’s aggressive design schedules.”
A PrimeTime Special Interest Group (SIG) event will be held on March 26th during SNUG® (Synopsys Users Group) Silicon Valley in Santa Clara, Calif., to highlight the new timing features. PrimeTime R&D will present the PrimeTime ADV technologies, and timing experts will share their experiences.
Availability
PrimeTime ECO leakage recovery is available now. Physical-aware ECO will be available in the June 2013 PrimeTime release.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.
