industry news
Subscribe Now

CEVA Introduces MUST™ Multi-core System Technology, Adds Vector Floating-point Capabilities for CEVA-XC DSP Architecture Framework

MOUNTAIN VIEW, Calif., Feb. 19, 2013 /PRNewswire/ — CEVA, Inc. (NASDAQ: CEVA), the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today announced a suite of advanced  processor and multi-core technologies to further enhance the CEVA-XC DSP architecture framework for high performance wireless applications including wireless terminals, small cells, access points, metro and macro base-stations. Among the new enhancements are: comprehensive multi-core features, high-throughput vector floating-point processing and a complete set of co-processor engines offering power-efficient hardware-software partitioning. CEVA has collaborated closely with leading OEMs, wireless semiconductors and IP partners for the definition and optimization of these technologies.

J. Scott Gardner, Senior Analyst at The Linley Group, commented: “In addition to improving performance while reducing cost and power consumption in wireless baseband designs, the new enhancements to the CEVA-XC architecture offer SoC designers a comprehensive environment to develop and optimize high-speed data flow in multi-core designs. Furthermore, the use of ARM’s latest interconnect and coherency protocols, together with advanced automated data traffic managers, as well as a dynamic scheduling software framework, position CEVA as the only DSP licensor today offering such extensive support for multi-core DSP-based SoCs. When combined with vectorized floating-point support and a wide range of coprocessor engines, the CEVA-XC architecture framework includes all the essential DSP platform components for a wide range of user equipment and infrastructure applications. 

MUST™ – advanced multi-core system technology

CEVA’s MUST™ is a cache-based multi-core system technology with advanced support for cache coherency, resource sharing and data management. Initially available for the CEVA-XC, MUST™ supports the integration of multiple CEVA-XC DSP cores in a symmetric multiprocessing or asymmetric multiprocessing system architecture, along with a broad range of technologies designed specifically for multi-core DSP processing. These technologies include:

  • Dynamic scheduling using shared pools of tasks,
  • Hardware event based scheduling defined via software,
  • Task and data driven shared resource management,
  • Advanced  memory hierarchy support with full cache coherency,
  • Advanced automated data traffic management without software intervention, and
  • Special prioritization scheme based on task-awareness.

To facilitate the development of advanced multi-core SoCs containing ARM® processors and multiple CEVA DSPs, CEVA has added extensive support to the CEVA-XC architecture framework for the ARM AXI4 interconnect protocol and AMBA 4 ACE cache coherency extensions. This dramatically simplifies the software development and debugging process for SoC designs, while also reducing the software cache management overhead, processor cycles and external memory bandwidth. The overall outcome is much tighter integration between the processors in the SoC, resulting in improvements in energy-efficiency and performance for the entire system.

Full support for vectorized floating-point operations

The LTE-Advanced and 802.11ac standards leverage multiple input multiple output (MIMO) processing, where the system utilizes multiple antennae to transmit and receive data. In order to achieve ultra-high precision and optimal performance when processing these complex data streams, CEVA has added support for floating-point operations to the CEVA-XC vector processor unit, in addition to the traditional fixed-point capabilities. Floating-point operations are supported on full vector elements, processing up to 32 floating point operations in every core cycle to meet the performance requirements of even the most demanding wireless infrastructure applications. In addition to these enhancements, CEVA has further extended its technology leadership with a dedicated instruction set architecture (ISA) for high-dimension MIMO, including support for 802.11ac 4×4 use cases.

Complete set of ultra-low power coprocessors for wireless modems

To further optimize advanced wireless systems for low power and performance, CEVA has introduced a comprehensive set of tightly-coupled extension (TCE) coprocessor units. These coprocessors address functions of the modem where greater performance can be achieved through the use of hardware that is tightly coupled with the CEVA-XC. CEVA’s TCEs now include:

  • Maximum Likelihood MIMO Detectors (MLD),
  • 3G de-spreader units,
  • FFT with NCO phase correction,
  • DFT,
  • Viterbi,
  • HARQ combining, and
  • LLR compression / de-compression

These tightly-coupled extensions are complemented by a unique automated low-latency data traffic management between the DSP memory and the coprocessors to minimize DSP intervention and enable a truly parallel co-processing capability. CEVA offers these TCEs as part of fully integrated and optimized modem reference architectures for licensees targeting user equipment, infrastructure and Wi-Fi applications, serving to lower the overall power consumption and significantly reduce customers’ development costs and time to market.

Eran Briman, vice president of marketing at CEVA commented: “The suite of technologies introduced today for the CEVA-XC will serve to vastly improve the performance, power consumption and time-to-market for multi-core DSP SoC designs targeting wireless applications. We collaborated closely with industry leaders in the handset and infrastructure markets throughout the specification process, ensuring our IP exceeds the stringent specifications required by the wireless industry. The combination of our MUST multi-core system technology, vector floating-point operation support, full support for ARM’s latest interconnect protocols and the large set of function-specific tightly-coupled extensions further reinforces our unrivalled leadership in DSP technologies for communications and provides a comprehensive solution for the development of high performance systems for LTE-Advanced, Wi-Fi and beyond.”  

About CEVA, Inc.

CEVA is the world’s leading licensor of silicon intellectual property (SIP) DSP cores and platform solutions for the mobile, portable and consumer electronics markets. CEVA’s IP portfolio includes comprehensive technologies for cellular baseband (2G / 3G / 4G), multimedia (vision, imaging and HD audio), voice processing, Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2012, CEVA’s IP was shipped in more than 1 billion devices, powering smartphones from many of the world’s leading OEMs, including HTC, Huawei, Lenovo, LG, Nokia, Motorola, Samsung, Sony, TCL and ZTE. Today, more than 40% of handsets shipped worldwide are powered by a CEVA DSP core. For more information, visit Follow CEVA on twitter at

Leave a Reply

featured blogs
Jun 13, 2021 Made in San Francisco Botanical Garden (camera Carey Guo) Monday: Hardware Hacking Party Tricks Tuesday: TSMC's 3DFabric Wednesday: Allegro X, the Design Platform for... [[ Click on the title to access the full blog on the Cadence Community ...
Jun 10, 2021
Data & analytics have a massive impact on the chip design process; we explore how fast/precise chip data analytics solutions improve IC design quality & yield. The post The Importance of Chip Manufacturing & Test Data Analytics in the Semiconductor Industry ap...
Jun 8, 2021
Samtec has hundreds of videos that span across everything from products, to demos, to presentations, branding, and more. We rebuilt our video search to be more lightweight, and also added a huge new feature. Previous to this update, all of the videos opened in a modal pop-up ...
Jun 7, 2021
By Calibre Staff Electrostatic discharge (ESD) is a big worry for integrated circuit (IC) designers,… The post ESD protection verification in 2.5/3D ICs is HARD (or is it?) Our on-demand webinar has the answer appeared first on Design with Calibre....

featured video

Industry’s First USB4 Silicon Success

Sponsored by Synopsys

USB4 offers up to 40Gbps speeds for incredibly fast connections. Join Synopsys to see the first demonstration of USB4 IP in silicon, along with real TX eyes for DesignWare USB4, DisplayPort, and USB 3.x IP.

Click here for more information about DesignWare USB4 IP

featured paper

An FAQ about the Matter connectivity standard from TI

Sponsored by Texas Instruments

Formerly Project CHIP, Matter is a new connectivity standard that runs on Thread and Wi-Fi network layers to provide a unified application layer for connected devices. Read this article to discover how you can get started with Matter and TI.

Click to read more

featured chalk talk

Cutting the AI Power Cord: Technology to Enable True Edge Inference

Sponsored by Mouser Electronics and Maxim Integrated

Artificial intelligence and machine learning are exciting buzzwords in the world of electronic engineering today. But in order for artificial intelligence or machine learning to get into mainstream edge devices, we need to enable true edge inference. In this episode of Chalk Talk, Amelia Dalton chats with Kris Ardis from Maxim Integrated about the MAX78000 family of microcontrollers and how this new microcontroller family can help solve our AI inference challenges with low power, low latency, and a built-in neural network accelerator. 

Click here for more information about Maxim Integrated MAX78000 Ultra-Low-Power Arm Cortex-M4 Processor