industry news
Subscribe Now

New Release of Cadence Incisive Platform Doubles Productivity of SoC Verification

SAN JOSE, CA–(Marketwire – January 22, 2013) – 

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, todayintroduced a new version of its leading functional verification platform and methodologies, featuring a broad set of new and enhanced capabilities which double the productivity of SoC verification over the previous release. Incisive® 12.2 delivers 2x performance, a new Incisive Debug Analyzer product, new low-power modeling, and hundreds of additional features needed to perform effective verification of today’s complex intellectual property (IP) and SoCs.

For IP block-to-chip verification, enhancements include:

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, todayintroduced a new version of its leading functional verification platform and methodologies, featuring a broad set of new and enhanced capabilities which double the productivity of SoC verification over the previous release. Incisive® 12.2 delivers 2x performance, a new Incisive Debug Analyzer product, new low-power modeling, and hundreds of additional features needed to perform effective verification of today’s complex intellectual property (IP) and SoCs.

  • Doubled performance from the simulator engine
  • Improved debug capabilities with the recently introduced Incisive Debug Analyzer
  • Automated Register Validation App that replaces hundreds of functional tests with a single formal analysis run
  • Simplified coverage data analysis with the new Incisive Metrics Center feature

At the SoC level, Incisive 12.2 has greater capacity for longer running simulations, including those incorporating low-power and mixed-signal designs.

For SoC verification, enhancements include:

  • An enhanced low-power algorithm in the simulator that delivers a 2x improvement in elaboration time. The new Incisive technology accurately models shutdown and recovery in low-power designs
  • An integrated digital-centric mixed-signal solution that uses real number models (RNM), resulting in simulation speed increases of over 300x using wreal or SystemVerilog-RNM types
  • Accelerated block and toggle coverage supported in Palladium XP Simulation Acceleration, reducing test time from hours to minutes

“Performance, scalability, and efficiency define our high-density switches,” said Fred Homewood, chief technology officer and founder of Gnodal Ltd, which plans to deploy the Incisive 12.2 release to its team in 2013. “The Incisive Platform and support team embodies these qualities, leading us to substantially increase our Incisive Enterprise Simulator licenses and deploy the Incisive Enterprise Manager and Incisive SimVision debug. We are implementing the metric-driven verification methodology and will use its automated verification planning capability to demonstrate our development productivity to our customers.”

“Some of our customers are building 200 million-gate SoCs — even larger — at advanced nodes,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “The successful verification of these designs is critical, and it requires the coordination of distributed worldwide teams. Unmatched in the breadth of its technology, Incisive 12.2 provides the productivity improvements these teams need to bring their designs to market fast and at high quality.”

The new Incisive release integrates with Cadence® verification IP for SoC verification, the Cadence Virtual System Platform for system verification, and the Palladium® XP for acceleration which includes the ability to hot-swap between software-based simulation and hardware-based acceleration.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Leave a Reply

featured blogs
Jan 17, 2022
Today's interview features Dajana Danilovic, an application engineer based near Munich, Germany. In this video, Dajana shares about her pathway to becoming an engineer, as well as the importance of... [[ Click on the title to access the full blog on the Cadence Community sit...
Jan 13, 2022
See what's behind the boom in AI applications and explore the advanced AI chip design tools and strategies enabling AI SoCs for HPC, healthcare, and more. The post The Ins and Outs of AI Chip Design appeared first on From Silicon To Software....
Jan 12, 2022
In addition to sporting a powerful processor and supporting Bluetooth wireless communications, Seeed's XIAO BLE Sense also boasts a microphone and a 6DOF IMU....

featured video

Synopsys & Samtec: Successful 112G PAM-4 System Interoperability

Sponsored by Synopsys

This Supercomputing Conference demo shows a seamless interoperability between Synopsys' DesignWare 112G Ethernet PHY IP and Samtec's NovaRay IO and cable assembly. The demo shows excellent performance, BER at 1e-08 and total insertion loss of 37dB. Synopsys and Samtec are enabling the industry with a complete 112G PAM-4 system, which is essential for high-performance computing.

Click here for more information about DesignWare Ethernet IP Solutions

featured paper

USB-C and USB Power Delivery Solutions

Sponsored by Analog Devices

Every electronic market is rapidly adopting the latest USB Type-C® and USB Power Delivery (USB-PD) specifications. The new USB Type-C cable and connector specifications dramatically simplify the way we interconnect and power electronic gadgets. With the proliferation of battery-operated devices for consumer, medical, automotive, and industrial applications, USB-C is increasingly becoming the preferred universal standard for charging and powering devices.

Click here to read more

featured chalk talk

FPGAs Advance Data Acceleration in the Digital Transformation Age

Sponsored by Achronix

Acceleration is becoming a critical technology for today’s data-intensive world. Conventional processors cannot keep up with the demands of AI and other performance-intensive workloads, and engineering teams are looking to acceleration technologies for leverage against the deluge of data. In this episode of Chalk Talk, Amelia Dalton chats with Tom Spencer of Achronix about the current revolution in acceleration technology, and about specific solutions from Achronix that take advantage of leading-edge FPGAs, design IP, and even plug-and-play accelerator cards to address a wide range of challenges.

Click here for more information