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Calypto Leverages Core Technology to Expand Product Portfolio, Announces Catapult Low-Power High-Level Synthesis

SANTA CLARA, Calif., – May 29, 2012 – Calypto® Design Systems, Inc., a leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) low power optimization, today announced Catapult®Low-Power (LP), the industry’s first production quality, high-level synthesis (HLS) tool that adds power as an optimization goal. By leveraging Calypto’s existing best in class power analysis and optimization technology, Catapult LP provides a closed loop optimization across power, performance and area (PPA) to address the challenges of power-aware design.

Catapult LP takes advantage of Calypto’s unique PowerPro® technology by embedding it “under the hood” of Catapult to seamlessly produce the lowest power RTL and optimize designs at the architecture level where 80% of power decisions are made.  For the first time, Catapult LP enables designers to explore different hardware architectures and measure the power, performance and area of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver closed loop PPA optimization from high-level synthesis. Catapult LP goes beyond the architecture level by leveraging Calypto’s patented sequential analysis technology to deliver automatic fine grain clock gating. This two prong approach of optimizing the architecture followed by maximum clock gating efficiency at the register level promises the greatest power savings. 

“In September 2011 Catapult merged with Calypto Design Systems, and today’s announcement of combining Catapult with Calypto’s PowerPro technology ‘under the hood’ demonstrates why the merger is good for our customers,” said Shawn McCloud, Vice President of Marketing at Calypto.  “Combining low-power with Catapult’s already proven track record of over 100 customers, 1000+ ASIC tapeouts, the industry’s widest language support, largest capacity, and #1 market position 5 years running creates a very compelling solution.”

In addition to Catapult LP, Calypto is also announcing PowerPro Power Analyzer (PA) 6.0, which adds production ready power analysis.  PowerPro PA provides RTL power estimation within 15% of gate level in a fraction of the time. With PowerPro PA designers can quickly estimate block-level power such as dynamic, leakage, peak, average and generate toggle activity reports.  Combining PowerPro PA with Calypto’s PowerPro optimization platform creates an extremely comprehensive, low-power flow across the entire SoC platform.

Design Automation Conference (DAC)

Catapult LP and PowerPro PA will be demonstrated at the Design Automation Conference (DAC) next week inSan Francisco (booth #1226).

About Calypto’s Products

Catapult high-level synthesis, SLEC® (Sequential Logic Equivalence Checking) and PowerPro platforms are used to design, verify and optimize complex SoC and FPGA designs by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of their SoC while significantly reducing overall design and verification time.

About Calypto

Calypto Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.

Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE?SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.

More information can be found at www.calypto.com.

 

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