Grenoble, France and San Jose, CA – February 29 , 2012 – Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today announced the release of its AceThermalModeler™ (ATM) software, a solution for generating compact thermal models for System on Chips (SoCs), 3D ICs, Systems in Package (SiPs) or complete boards.
Compact thermal models enable early system floorplan exploration or partitioning, new system packaging and integration architectures, and early exploration of power management policies to reduce temperature’s peaks, and manage temperature gradients across the system.
ATM bridges the gap between thermal experts and the system architecture teams to improve productivity. With ATM, thermal experts can give system architects a solution that generates RC compact thermal models that are fast to create and simulate. The system architecture team can then work autonomously to estimate various corner use cases, floorplans, architecture options for multi-core designs, operating points or power management policies impact on temperature across the system.
Ghislain Kaiser, CEO, Docea Power, commented: “We anticipated very early that temperature will become a challenge for next generation devices. Because of this, we developed a simulator that closes the loop between power and temperature for the first versions of Aceplorer™, our solution for Electronic System Level power modeling and optimization. Now, we complete the flow with ATM, a tool that is easy to use and generates thermal models. With it, system architects can perform both thermal steady state or coupled power and thermal analysis for dynamic application profiles running on different architecture configurations.”
ATM will be demonstrated at the Design, Automation & Test (DATE) conference in Dresden, Germany, March 12 to 16, 2012.
About the Need for Thermal Models
Thermal issues are a common challenge to a wide spectrum of electronics applications, from industrial and transportation to wireless chipsets and networking ICs. For all these applications, thermal issues found late in the design cycle translate in additional costs and poor yield or product reliability. Any rework means heavy impact on time-to-market. Enabling early dynamic or steady state estimations of thermal distributions for the most power hungry use cases allows system architects to optimize systems and architectures and avoid loss of revenue due to thermal issues found late in the project.
About Docea Power
Docea Power develops and commercializes a new generation of methodology and tools for enabling faster more reliable power and thermal modeling at the system level. Based on itsAceplorer platform, the Docea Power solution uses a consistent approach for executing architecture exploration and optimizing power and thermal behavior of electronic systems at an early stage of an electronic design project. The company has offices near Grenoble, France, and in San Jose, California, USA, and sales offices in Japan and Korea. For more information, please visit www.doceapower.com.
