industry news
Subscribe Now

Si2 Organizes 3D Panel at DesignCon 2012

DesignCon 2012 — AUSTIN, Texas — The Silicon Integration Initiative (Si2) announced today the “Why Do We Need 3D Design Standards” panel session at DesignCon 2012. This panel will be held on Tuesday, January 31 in Ballroom E at the Santa Clara Convention Center, Santa Clara, CA, from 3:45 PM to 5:00 PM.

This panel will explore whether the design community needs 3D IC standards to accelerate the adoption of 3D design, and if so, how the standards can be implemented, the priority of these required standards, what are the challenges in doing so and how to get started. It will also provide insights on how the many different industry groups are working together to prevent overlapping efforts or missing critical areas. In a typical 3D IC, functional tiers will likely be coming from different companies and at different process nodes, and possibly different foundries as well. Without effective standards, it is difficult to efficiently integrate different tiers into a common package using best-in-class tools from multiple vendors and test the result. It is not possible to ensure a single EDA vendor flow spanning across the design of tiers designed by different companies.

The Panelists include:

Sumit DasGupta, Sr. VP, Si2

Riko Radojcic, Director, Qualcomm

Liam Madden, Corporate VP FPGA Development and Silicon Technology, Xilinx

Raj Jammy, Vice President of Materials and Emerging Technologies, SEMATECH

Jim Hogan, Investor, Telos Venture Partners

Bryon Moyer, Writer/editor, Techfocus Media

For more information on the Panel click here: http://schedule.designcon.com/session/6396

For a free DesignCon 2012 Expo Pass and Conference discount, click here: http://www.si2.org/?page=1516

About Si2

Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 24th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 90 companies involved in all parts of the silicon supply chain throughout the world. See www.si2.org

Leave a Reply

featured blogs
May 17, 2022
'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF Solution and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now,... ...
May 17, 2022
Explore Arm's SystemReady program, and learn how we're simplifying hardware/software compliance through pre-silicon testing for Base System Architecture (BSA). The post Collaborating to Ensure that Software Just Works Across Arm-Based Hardware appeared first on From Silicon ...
May 12, 2022
By Shelly Stalnaker Every year, the editors of Elektronik in Germany compile a list of the most interesting and innovative… ...
Apr 29, 2022
What do you do if someone starts waving furiously at you, seemingly delighted to see you, but you fear they are being overenthusiastic?...

featured video

Intel® Agilex™ M-Series with HBM2e Technology

Sponsored by Intel

Intel expands the Intel® Agilex™ FPGA product offering with M-Series devices equipped with high fabric densities, in-package HBM2e memory, and DDR5 interfaces for high-memory bandwidth applications.

Learn more about the Intel® Agilex™ M-Series

featured paper

Real-time Cloud Application Execution with Remote Data

Sponsored by Intel

Intel® Partner Alliance member, Vcinity, enables hybrid and multi-cloud applications secure, real-time access to data anywhere to flexibly accelerate time to insights and business outcomes.

Click to read more

featured chalk talk

"Scalable Power Delivery" for High-Performance ASICs, SoCs, and xPUs

Sponsored by Infineon

Today’s AI and Networking applications are driving an exponential increase in compute power. When it comes to scaling power for these kinds of applications with next generation chipsets, we need to keep in mind package size constraints, dynamic current balancing, and output capacitance. In this episode of Chalk Talk, Mark Rodrigues from Infineon joins Amelia Dalton to discuss the system design challenges with increasing power density for next generation chipsets, the benefits that phase paralleling brings to the table, and why Infineon’s best in class transient performance with XDP architecture and Trans Inductor Voltage Regulator can help power  your next high performance ASIC, SoC or xPU design.

Click here for more information about computing and data storage from Infineon