SANTA CLARA, Calif., October 12, 2011 – MoSys, Inc., (NASDAQ: MOSY), a leading provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, announces the availability of its Bandwidth Engine® FPGA Companion Kit and Characterization Kit.
These Bandwidth Engine development kits allow system designers to evaluate and develop code for next-generation networking systems that incorporate Bandwidth Engine ICs. The FPGA Companion Kit includes a MoSys Bandwidth Engine evaluation board with FCI AirMax VS® connectors arranged in accordance to Interlaken Physical Interop Recommendations, which allow for integration with standard FPGA 100G development kits.
The Characterization Kit contains a board populated with SMA connectors to interface to any suitable FPGA or ASIC development system purpose of SerDes evaluation, the Characterization Kit can be operated in loopback mode connected to high-performance test equipment.
Both kits allow for connection of all 16 OIF CEI-11 compatible SerDes lanes that operate at up to 10.3125 Gbps and communicate with the host using the GigaChip™ Interface. The boards are available with either a test socket or with a Bandwidth Engine IC soldered onto the board.
“MoSys’ FPGA Companion Kit and Characterization Kit enable customers to evaluate Bandwidth Engine ICs and develop products on fully-functional hardware platforms,” stated David DeMaria, Vice President of Business Operations. “This is an important milestone in enabling our customers to incorporate Bandwidth Engine ICs into their next generation of products.”
About MoSys, Inc.
MoSys, Inc. (NASDAQ: MOSY) is a leading provider of high-performance networking memory solutions and high-speed, multi-protocol serial interface intellectual property (SerDes IP). MoSys’ leading edge Bandwidth Engine® ICs combine the company’s patented 1T-SRAM® high-density memory with its SerDes IP and are initially targeted at providing breakthroughs in bandwidth and access performance in next generation networking systems. MoSys’ SerDes IP and DDR3 PHYs support a wide range of data rates across a variety of standards, while its 1T-SRAM memory cores provide a combination of high-density, low-power consumption, high-speed and low cost advantages for high-performance applications. MoSys is headquartered in Santa Clara, California. More information is available on MoSys’ website at www.mosys.com.
