IMS 2011 – Baltimore, Maryland – June 7, 2011 – Intercept Technology, Inc., a leader in PCB/Hybrid/RF electrical engineering applications, today announced benchmark design performance increases of up to 75x using the latest enhancements in its Pantheon PCB/Hybrid/RF layout design application. In some areas, the improvements reached over 100x faster, giving Intercept software unprecedented speed improvements on the largest and most complex designs seen to date.

The performance increases are most notable in designs using Intercept’s block technology, which provides endless opportunities to shorten design cycle times and reduce repetitive edits by allowing full or partial board circuitry to be defined as a block and intelligently placed one or more times into another block, board, or panel. Additionally, Pantheon supports placement of any number of sub-blocks within main blocks, which allows reusable circuitry to be maintained and edited separately throughout many levels of a design. These blocks maintain full connectivity with the schematic at all levels of board hierarchy, while also allowing edits and automatic updates to blocks at any level on the fly.

In one of the performance test benchmarks, Intercept worked closely with an RF customer to prove a test array panel of 16 top level designs, each containing 64 identical, replicated blocks, for a total of 1024 intelligent hierarchical blocks. Results demonstrated that edits made to a single block populated across the board 1024 times took just over one minute to update on the entire panel array. Likewise, all design tasks found to cause performance delays were reduced to similar, more reasonable performance times. On less complex designs, the performance increases are even more pronounced.