Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced it has collaborated with TSMC to deliver their customers DFM expertise and technology in a service model. In an effort to reduce risk and enable the fastest path to Silicon Realization, Cadence DFM Services include model-based simulation of litho-process checks and virtual chemical mechanical polishing for TSMC 40-nanometer technology and below. The goal is to enable design teams to effectively get help in detecting litho or CMP hotspots in order to fix them prior to tapeout. Cadence is the first EDA partner certified by TSMC for DFM services.
“At 40 nanometers and below, it is essential that design teams take DFM issues into account throughout the design process,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “DFM services from Cadence are a key milestone of our long-term collaboration with Cadence to help our common customers to address critical design needs in advanced technologies.”
With the increased manufacturing challenges inherent at smaller geometries, DFM checks are an essential part of design flows at 40 nanometers and below. TSMC’s collaboration with Cadence in DFM services is the latest in a continuum of joint efforts by the two companies to address manufacturing challenges for the most cutting-edge designs.
“Tilera is at the leading edge of innovation in the multi-core processor market, with devices coming out this year containing up to 100 cores on a single chip,” said John F. Brown III, vice president of IC Engineering at Tilera Corp. “To meet our time-to-market goals, we needed a fast turnaround time solution for the foundry-mandated litho checks. We teamed with Cadence because it was important for us to use a proven solution with a long track record of silicon success. Cadence offered the best cost of ownership and provided the technical expertise to achieve our design cycle-time goals. We are extremely satisfied with the Cadence holistic DFM services.”
Cadence DFM Services offer engineering expertise gained over many years of collaboration between the two leading companies. Customers get turnkey access to DFM analysis based on TSMC’s DFM Data Kit (DDK) to ensure needed accuracy, and DFM Services output analysis reports, which enable fixing in Encounter® Digital Implementation System or Virtuoso® custom/analog implementation technologies. Cadence DFM Services deliver a scalable and secured IT infrastructure that helps reduce the risk of schedule slips while optimizing time to volume.
“TSMC and Cadence have long seen eye to eye on the need for enabling engineers to address DFM issues in a timely way, at lower cost and lower risk,” said David Desharnais, group director, product marketing, Silicon Realization at Cadence. “With the collaboration with TSMC, Cadence is offering both the expertise and the technology our customers need to deploy the type of holistic approach to Silicon Realization that’s at the heart of the EDA360 vision.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
