industry news
Subscribe Now

VIA Technologies Adopts Mentor Graphics Calibre PERC for Critical ESD Checkin

WILSONVILLE, Ore., February 7, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced that VIA Technologies, Inc., a fabless supplier of power efficient x86 processor platforms, is adopting the Calibre® PERC electrical rule checking product to ensure that electrostatic discharge (ESD) protection meets established guidelines to help prevent circuit failures and design re-spins.

By helping ensure that designers have met all ESD protection rules, the Calibre PERC product contributes to the robustness of designs in portable and high-reliability applications. It also verifies the integrity of low-power designs that have multiple-power domains by making a variety of leakage and resistance checks. The Calibre PERC product removes the burden of manual electrical rule checking from designers, as it can be programmed to meet these general concerns as well as address unique customer requirements.

“Calibre PERC is the only tool that enables users to define electrical checks using both topology and geometric information. We use this tool to create a set of rules that preserve debugging experience from previous product ESD issues and prevent the same ESD failures from happening across many design sites,” said Shelton Lu, Vice President of Manufacturing and Product Engineering in the CPU Platform R&D division of VIA. “This allows PERC to perform many critical checks for our design engineers. VIA has a very sophisticated methodology for how our ESD structures should be constructed, including rules for multiple power domains, back-to-back diodes and power/ground clamp devices. Additionally, we also have checks that we perform on leakage paths and discharge path resistance. PERC provides our designers a solution to validate the robustness of our designs by giving us access to the necessary circuit, geometry and parasitic information to automatically perform checks that help drive the reliability of VIA’s product offering.”

“Our customers need to automate very complex electrical design rule checks in a multi-voltage, mixed-signal environment,” said Joseph Sawicki, Vice President and General Manager for the Design-to-Silicon division at Mentor Graphics. “Calibre PERC introduces a new class of design rule checkers that provide our customers with the versatility and programmability needed for today’s advanced designs, while working in the familiar Calibre platform that is integrated into all major EDA design flows and supported by all the major foundries.”

Availability

The Calibre PERC product is available now with support for TSMC, Common Platform and SMIC.

About Calibre PERC

The Calibre PERC product addresses a range of applications including validating that a circuit has sufficient protection against electrostatic discharge (ESD) events, and helping designers identify inappropriate connections between multiple power supplies in mixed-signal ICs. It helps ensure the completeness of circuitry needed to protect a device against ESD and ensures a higher level of ESD design rule compliance because it goes beyond traditional layout geometry-based checking to enable verification of specific device and interconnect structures and electrical characteristics. For example, it can identify the omission of required ESD protection on a schematic or netlist. It can also be used to look for errant signal paths and other soft connection errors such as well connection errors, floating devices, nets, or pins, incorrect voltage supply connections, excessive series pass gates, problem level shifter designs, antenna checks, floating wells, minimum “hot” NWELL width, and many others.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

Leave a Reply

featured blogs
Apr 24, 2024
Learn about maskless electron beam lithography and see how Multibeam's industry-first e-beam semiconductor lithography system leverages Synopsys software.The post Synopsys and Multibeam Accelerate Innovation with First Production-Ready E-Beam Lithography System appeared fir...
Apr 24, 2024
Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified through our culture at Cadence. In the DEI@Cadence blog series, you'll find a community where employees share their perspectives and experiences. By providing a glimpse of their personal...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

The Future of Intelligent Devices is Here
Sponsored by Alif Semiconductor
In this episode of Chalk Talk, Amelia Dalton and Henrik Flodell from Alif Semiconductor explore the what, where, and how of Alif’s Ensemble 32-bit microcontrollers and fusion processors. They examine the autonomous intelligent power management, high on-chip integration and isolated security subsystem aspects of these 32-bit microcontrollers and fusion processors, the role that scalability plays in this processor family, and how you can utilize them for your next embedded design.
Aug 9, 2023
30,451 views