industry news
Subscribe Now

Synopsys Announces New Technology for Optimizing Multicore Systems

MOUNTAIN VIEW, Calif., Feb. 7, 2011 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the broad availability of Platform Architect with Multicore Optimization Technology, a new solution for performance analysis and early definition of multicore system architectures in SystemC. Using Platform Architect with Multicore Optimization Technology, designers of SoCs, chipsets and systems can capture hardware/software performance models of multicore system architectures in the early concept phase for robust performance measurement and trade-off analysis, months prior to software availability.

“Given the escalating costs of SoC design, system architects have a difficult task in defining the optimum system architecture to support all the desired application use-cases in a cost-effective way,” says Rene van den Berg, system architect, car entertainment solutions, NXP Semiconductors. “The new Multicore Optimization Technology embedded in Synopsys’ Platform Architect gives architects a clear understanding of the application and required features in an early stage of the project. With this insight on system performance, the hardware and software allocation of available resources, software scheduling scenarios and architecture dimensions and decisions, the overall design cycle time is greatly reduced.”

The new Multicore Optimization Technology enables Platform Architect users to create task-driven workload models of the end-product application, known as task-graphs, enabling analysis and optimization of hardware/software partitioning and system performance. After hardware/software partitioning is finalized, architects reuse the same task-graphs and task-driven traffic for SoC-level architecture exploration and IP selection, as well as interconnect and memory subsystem performance optimization. Benefits include optimized multicore system performance, shorter evaluation times and faster time-to-market.

“Developers of multicore SoCs, chipsets and systems often tell us how worried they are about the risks of over-design and under-design, causing either uncompetitive products or expensive re-spins. They are realizing that multicore architecture analysis needs to be much more robust and start much earlier,” says Frank Schirrmeister, director of product marketing, System-Level Solutions, Synopsys. “The new Multicore Optimization Technology for Platform Architect allows our users to find and resolve multicore performance issues while architecture changes are still feasible, avoiding costly re-work to hardware and software implementations.”

Interaction between providers of hardware and software IP, multicore SoCs, chipsets and systems have become increasingly complex. Multicore Optimization Technology for Platform Architect greatly improves the effectiveness and precision of this collaboration by replacing written and verbal specifications with executable performance models of multicore system architectures. These can be easily shared between design chain partners without depending on final software and hardware.

Availability

Multicore Optimization Technology for Platform Architect is available effective immediately as an option for customers of Platform Architect.  For more information on Platform Architect please visit http://synopsys.com/platformarchitect.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Leave a Reply

featured blogs
Dec 8, 2023
Read the technical brief to learn about Mixed-Order Mesh Curving using Cadence Fidelity Pointwise. When performing numerical simulations on complex systems, discretization schemes are necessary for the governing equations and geometry. In computational fluid dynamics (CFD) si...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Challenges of Multi-Connectivity Asset Tracking
Multi-connectivity asset tracking is a critical element of our modern supply chain. In this episode of Chalk Talk, Colin Ramrattan and Manuel Cantone from STMicroelectronics and Amelia Dalton discuss the common needs required for asset tracking today, why low power processing is vital for these kind of applications, and how STMicroelectronics ASTRA platform can help you get started on your next asset tracking design.
Feb 20, 2023
34,367 views