WHAT: Jasper Design Automation’s ActiveProp™ property synthesis tool will make its North American debut at this year’s DVCon. ActiveProp automatically synthesizes properties to expand the property verification set, increase functional coverage, and identify coverage holes. Jasper is also highlighting its industry-leading formal solutions, including JasperGold®, ActiveDesign™ and Intelligent Proof Kits that speed the verification of SoC interconnect protocols. Jasper’s advanced technology addresses verification challenges across the spectrum of design applications from architectural verification to post-silicon validation.
WHEN: DVCon will be held Feb. 28 – March 3.
Exhibits are open Tuesday and Wednesday, March 1-2, 2pm-6:30pm.
WHERE: Jasper Booth #704, DoubleTree Hotel, San Jose, Calif.
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 200 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.
