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Tanner EDA to Address Some of the Key Challenges Facing Analog Designers at DesignCon 2011

MONROVIA, California – January 25, 2011 – At DesignCon 2011, Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), will continue their focus on accelerating analog design in a panel session on process design kits (PDKs) for analog designers and in a presentation on breaking through the analog IC layout design bottleneck. DesignCon 2011 takes place from January 31st to February 3rd in the Santa Clara Convention Center, Santa Clara, CA.



75-minute technical panel session “PDKs for Analog IC Design – A Stakeholder Discussion.” PDKs are an essential component of the analog designers’ toolkit. Recent industry initiatives aimed at defining PDK standards and reducing the PDK maintenance overhead have been largely focused on process nodes that are biased towards leading-edge digital designs. The result is that analog designers are at risk of having the standards and process rules not meet their requirements. This panel discussion will outline and explore some of the key challenges facing analog designers related to PDKs. Opinions, perspectives and proposed mitigation strategies will be expressed by representatives from key stakeholder groups: designers, EDA tool vendors, and foundries.


Moderator: Daniel Nenni, strategic foundry relationship expert for companies wishing to partner with Global Foundries, SMIC, TSMC, and UMC and blogger on

Panelists: Yaron Kretchmer — Senior Manager, SJ Backend CAD, Altera

John Stabenow — Group Director, Custom/Analog Product Management, Cadence Design      Systems

Tom Quan — Design Methodology & Service Marketing (DMSM)

Ed Lechner – Director, Product Marketing, Synopsys

Mass Sivilotti — Chief Scientist, Tanner EDA

Samir Chaudhry – Director, Design Enablement, TowerJazz Semiconductor

When: Wednesday, February 2nd, from 3:45 – 5:00pm Pacific

Where: Ballroom F

For additional information, see



Participants in this session will learn about the business and technological conditions that have led to analog IC layout becoming a bottleneck in the chip design process. After a brief review of prior attempts to address this challenge, a new paradigm for overcoming this bottleneck will be introduced. The session will conclude with a live demonstration of a new design tool that creates key device structures (differential pairs and current mirrors) that accelerate analog IC design layout in CMOS. The presenters will show how the tool works within an existing design workflow and how the resulting structures are high-quality and DRC/LVS clean. The session will conclude with a summary of current tool users’ results with special focus on improved quality and reduced cycle time.


Jeff Miller, Director of Product Management, Tanner EDA and John Zuk, Vice President of Marketing and Strategy, Tanner EDA

When: Wednesday, February 2nd, from 8:30am – 9:10 am Pacific

Where: Room 210

For additional information, see

About Tanner EDA

Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

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