industry news
Subscribe Now

Mentor Graphics Calibre PERC Programmable Electrical Rule Checker Improves Fujitsu Chip Reliability

WILSONVILLE, Ore., January 25, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced that Fujitsu Semiconductor Limited is now using the Calibre® PERC product for electrical rules checks that improve the correctness and reliability of its IC designs before committing to manufacturing. The product, which automates electrical checks based on user-defined rules, is designed to address customers’ need to improve reliability by identifying areas of vulnerability to catastrophic electrical failures in ICs during factory test, transport, and field operation. Among the specific checks being performed at Fujitsu Semiconductor are electrostatic discharge (ESD) protection circuit checking, cross-domain and multi-cross-domain protection checking, level shifter checking, and optimal ESD I/O placement checking.

According to Masaru Ito, Director of System LSI Technology & Product Department, Technology Development Division, IP & Technology Development and Manufacturing Unit at Fujitsu Semiconductor Limited, “In the past we have used a combination of visual layout inspection and custom scripts to find issues associated with circuitry to protect against ESD events and to support multiple voltage domains. Of course, this was very time consuming and not very reliable. We found the combination of features in Calibre PERC combined with its extensive programmability allowed us to define and perform all the checks we need to make, and it gives us the flexibility we need to adapt to future requirements. Initially, we are using Calibre PERC for a part of our design technology, and in the future we will expand usage to all IC development in order to improve overall product reliability and verification efficiency.”

“Calibre PERC gives IC designers a new tool to address reliability challenges by assessing critical circuits both geometrically and electrically, while greatly reducing the manual time and effort required for verification,” said Joseph Sawicki, Vice President and General Manager of Mentor’s Design-to-Silicon division. “Its programmability also gives PERC a unique ability to adapt to multi-voltage, mixed-signal environments and continue to grow with customer needs.”

About Calibre PERC

The Calibre PERC product addresses a range of electrical rule checking (ERC) applications with extensive programmability and the unique ability to perform verification based on combined information from the netlist and the layout topology. This enables complex checks such as identifying the omission of required ESD protection on a schematic or netlist. It can also be used to look for errant signal paths and other soft connection errors such as well connection errors, floating devices, nets, or pins, incorrect voltage supply connections, excessive series pass gates, problem level shifter designs, antenna checks, floating wells, minimum “hot” NWELL width, and many others.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

Leave a Reply

featured blogs
Apr 6, 2020
My latest video blog is now available. This time I am looking at the use of dynamic memory in real-time embedded applications. You can see the video here or here: Future video blogs will continue to look at topics of interest to embedded software developers. Suggestions for t...
Apr 4, 2020
That metaphorical '€œboing'€ sound you hear, figuratively speaking, is a symbolical ball allegorically landing on Chewy'€™s side of the illusory net....
Apr 3, 2020
[From the last episode: We saw some of the mistakes that can cause programs to fail and to breach security and/or privacy.] We'€™ve seen how having more than one program or user resident as a '€œtenant'€ in a server in the cloud can create some challenges '€“ at leas...
Apr 2, 2020
There are many historical innovations that are the product of adversity, and the current situation is an extreme example.  While it is not the first time that humanity has faced a truly global challenge like the COVID-19 pandemic, this time the world is connected by tech...

Featured Video

LE Audio Over Bluetooth with DesignWare Bluetooth IP

Sponsored by Synopsys

The video shows the new LE Audio using Synopsys® DesignWare® Bluetooth 5.2 PHY IP and Link Layer IP with isochronous channels, and ARC® Data Fusion IP Subsystem with ARC EM9D Processor, running the LC3 codec supporting LE Audio.

Click here for more information about Bluetooth, Thread, Zigbee IP Solutions