Ottawa, Canada and Santa Clara, Calif.
What: Sidense exhibiting at Common Platform Technology Forum
Booth #103
Where: Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054
When: Tuesday, January 18, 2011
11:30AM to 6:30PM
Who: Jim Lipman, Sidense Marketing Director
For more information or to schedule a meeting with Sidense please contact:
Jim Lipman
Sidense
925-606-1370
About Sidense
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense SiPROM, SLP and ULP memory products, embedded in over 140 customer designs, are available from 180nm down to 40nm and are scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit www.sidense.com.
About Common Platform Technology Forum 2011
The Common Platform alliance of IBM, Samsung and GLOBALFOUNDRIES invites you to join us at our technology forum on January 18. This year’s event will focus on access to industry ready technology, proven design solutions and advanced technologies for high growth markets such as mobile and low power. Technical details of the innovative 28nm HKMG design for low-power applications will be revealed, along with technology advancements in SoC enablement solutions, materials science, process technology and manufacturing.
In addition, we’ll explore the invention process to bring about next-generation technology and the roadmap to 20nm. A key part of our forum will focus on technology delivery, and we will be highlighting our rich and broad ecosystem of design enablement and implementation partners in our Partner Pavilion.
