industry news
Subscribe Now

Synopsys’ DesignWare SuperSpeed USB 3.0 IP receives USB-IF certification

MOUNTAIN VIEW, Calif. – March 31, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its DesignWare(R) SuperSpeed USB (USB 3.0) Solution including Controller and PHY IP  successfully passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification. To achieve certification, the IP must pass protocol, electrical, and interoperability tests for SuperSpeed USB (USB 3.0, 5 Gbps) and Hi-Speed USB (USB 2.0, 480 Mbps). Synopsys created a fully integrated USB 3.0 IP solution, optimising all speed modes into a single USB 3.0 solution. This unique implementation enables designers to reduce area, pin count and power compared to separate USB 2.0 and SuperSpeed USB-only designs. Furthermore, the integrated DesignWare SuperSpeed USB IP significantly lowers integration risk and effort by not requiring designers to manage two distinct USB 2.0 and USB 3.0 data paths in their system-on-chips (SoCs). Synopsys will be showcasing its certified DesignWare SuperSpeed USB IP solution at the SuperSpeed USB Developer’s Conference, Booth #18, in Taipei on April 1-2, 2010.

“Passing certification is important as it demonstrates that the IP meets USB-IF interoperability standards and is compliant to the USB 3.0 specification,” said Jeff Ravencraft, president and chairman, USB-IF. “Certification of IP building blocks is an important step in the evolution of SuperSpeed USB technology, it assures designers that the solution interoperates with existing USB products while providing the speed and power benefits that SuperSpeed USB offers.”

“As a leading provider of graphics over USB 2.0, it was critical that we select a trusted USB IP provider for the development of our next generation high-definition over USB 3.0 platform,” said Dennis Crespo, executive vice president of marketing, DisplayLink. “We chose Synopsys because of their established track record in delivering proven and compliant USB IP solutions which enables us to reduce the risk of incorporating a new interface into our design and quickly get our differentiated product to the market.”

“For the past 15 years, Synopsys has been delivering high quality USB IP solutions which have been integrated in more than 2000 designs,” said John Koeter, vice president of marketing, Solutions Group at Synopsys. “We leveraged our extensive experience in USB 2.0 and high-speed serial interfaces to develop our USB 3.0 IP solution that supports all four transfer speeds defined in the USB 3.0 specification. This gives designers a reliable and low-risk path to silicon-success for their USB 3.0 products.”

The DesignWare SuperSpeed USB device controller and PHY IP are based on Synopsys’ technology leading Hi-Speed USB products, which have been silicon-proven in thousands of designs and are shipping in volume production. Optimised for low power, the DesignWare SuperSpeed USB device controller is architected to allow designers to maximise battery life by using dual power rails. The DesignWare SuperSpeed USB PHY consists of integrated high-speed digital and analogue blocks, PLL and I/O pads, which are delivered as GDSII for advanced foundry processes. This saves designers considerable time, cost and the risk of acquiring and integrating the IP separately. The DesignWare SuperSpeed USB Verification IP has built-in support for the VMM methodology, enabling designers to quickly verify connectivity between integrated IP and the SoC. The Linux drivers and SystemC(TM) transaction-level models in the DesignWare SuperSpeed USB virtual prototype allow designers to begin software development in parallel with IP integration, months before hardware and FPGA prototypes are ready. This significantly reduces the length of the product design cycle.


The DesignWare SuperSpeed USB Device, Hub, Host and Dual-Role Device Controllers, virtual prototype and driver IP are available now. The DesignWare SuperSpeed USB PHY IP is available in leading 65-nanometer (nm) and 130-nm process technologies now with support for 28-nm and 40-nm process technologies expected to be available in the second half of 2010. For more information on DesignWare USB IP, please visit: or follow our blog at

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven interface and analogue IP solutions for system-on-chip designs. Synopsys’ broad IP portfolio delivers complete connectivity IP solutions consisting of controllers, PHY and verification IP for widely used protocols including USB, PCI Express, DDR, SATA, Ethernet, HDMI and MIPI IP including 3G DigRF, CSI-2 and D-PHY. The analogue IP family includes Analogue-to-Digital Converters, Digital-to-Analogue Converters, Audio Codecs, Video Analogue Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transaction-level models to build virtual prototype for rapid, pre-silicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: Follow us on Twitter at

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at

Leave a Reply

featured blogs
Oct 15, 2021
We will not let today's gray and wet weather in Fort Worth (home of Cadence's Pointwise team) put a damper on the week's CFD news which contains something from the highbrow to the... [[ Click on the title to access the full blog on the Cadence Community site. ...
Oct 13, 2021
How many times do you search the internet each day to track down for a nugget of knowhow or tidbit of trivia? Can you imagine a future without access to knowledge?...
Oct 13, 2021
High-Bandwidth Memory (HBM) interfaces prevent bottlenecks in online games, AI applications, and more; we explore design challenges and IP solutions for HBM3. The post HBM3 Will Feed the Growing Need for Speed appeared first on From Silicon To Software....
Oct 4, 2021
The latest version of Intel® Quartus® Prime software version 21.3 has been released. It introduces many new intuitive features and improvements that make it easier to design with Intel® FPGAs, including the new Intel® Agilex'„¢ FPGAs. These new features and improvements...

featured video

Simplify building automation designs with MSP430

Sponsored by Texas Instruments

Smart building automation requires simple, flexible designs. With integrated, high-performance signal chain, MSP430 MCUs can enable high-accuracy motion detection, sensing and motor control to take performance and efficiency to the next level.

Click here for more information

featured paper

How to Design with Maxim’s Latest Supervisors

Sponsored by Maxim Integrated (now part of Analog Devices)

As the technologies in MCUs, µPs, DSPs, and FPGAs move toward lower geometries and power, operational voltages become significantly low for these devices. Reducing the core voltage poses challenges in the use of high-accuracy power supply and voltage supervisors to avoid system failure. This application note discusses the critical parameters Maxim’s MAX16132–MAX16135 supervisor family and presents a reasonable approach in choosing the right reset threshold and hysteresis for voltage supervisor ICs.

Click to read more

featured chalk talk

Yield Explorer and SiliconDash

Sponsored by Synopsys

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

Click here for more on the Synopsys Silicon Lifecycle Management Platform