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Synopsys’ New DesignWare Sonic Focus IP Solutions Deliver Exceptional Sound Through Standard Speakers

MOUNTAIN VIEW, Calif., Jan. 6, 2011 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of two new DesignWare™ Sonic Focus™ IP products that enable system-on-chip (SoC) designers and original equipment manufacturers (OEMs) to significantly enhance audio quality and deliver an immersive audio experience for a broad range of low power, DSP-based consumer electronics devices. The DesignWare Sonic Focus Stereo and Stereo HD (High-Definition) IP are audio post-processing solutions that help restore clarity, warmth, detail and realism to compressed digital audio content in consumer electronics devices. The Sonic Focus Stereo IP, targeted at low-power, portable devices such as handheld game consoles, mobile phones, docking stations and Bluetooth headsets, enables high-quality sound to be delivered through the smallest of speakers. The Sonic Focus Stereo HD IP delivers high-performance virtual surround sound for tethered stereo devices such as digital TVs, advanced stereo speakers, speaker sound bars and digital signal processing (DSP) enabled headphones.

As multimedia consumer electronics products get smaller and thinner, audio suffers tremendously due to the limited size of the speakers and audio cabinets. The DesignWare Sonic Focus Stereo and Stereo HD IP solutions help restore audio fidelity that is obscured by compression. They also overcome audio limitations due to creative industrial designs and recreate the original user experience from digital content. In addition, the Synopsys solutions include a robust set of components that enable designers to meet the performance, power and memory requirements of their stereo-enabled applications.

  • The DesignWare Sonic Focus Audio Software IP uses advanced, multi-channel internal processing algorithms, enabling devices to accept and process multi-channel stereo audio content (including 5.1 and 7.1 audio channel input modes) and reproduce a rich audio experience
  • The DesignWare Sonic Focus Surround IP expands the sound field of the device’s audio output, helping to create the desired immersive impact and effect from high-performance stereo products
  • The DesignWare Sonic Focus Product Mastering tools, which work directly with the embedded Sonic Focus audio algorithms, providing designers with real-time feedback and control of the audio software to create a high-quality audio experience

“DesignWare Sonic Focus Stereo post-processing IP has been successfully implemented by leading PC manufacturers to deliver a rich, compelling audio listening experience for end users,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “The Sonic Focus Stereo IP solutions extend this benefit into low-power DSP and cost-effective embedded stereo audio applications, delivering enhanced performance in ultra-thin speaker-based designs. In addition, by using the new Synopsys Sonic Focus logo on their products, OEMs and ODMs can further differentiate their leading consumer multimedia products that take advantage of this unique audio technology.”


The DesignWare Sonic Focus Stereo IP solutions are available now. For additional information, please visit To see the DesignWare Sonic Focus Stereo and Stereo HD IP demonstrations at CES 2011 visit Synopsys in the Venetian Suite exhibits, room 30-334.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and Verification IP for widely used protocols, analog IPembedded memorieslogic libraries, embedded test & repair IP, audio post-processing software and configurable processor cores. In addition, Synopsys offers SystemC transaction-level models to build virtual prototypes for rapid, pre-silicon development of software. With a robust IP development methodology, reuse tools, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: Follow us on Twitter at

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at

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Mentor Graphics Supports the Canon India Design Centre’s Migration to OVM

WILSONVILLE, Ore.–(BUSINESS WIRE)–Mentor Graphics Corporation (NASDAQ:MENT) today announced that the Canon India Design Centre has successfully deployed theQuesta® advanced verification platform with SystemVerilog as a next-generation HVL and Open Verification Methodology (OVM)-based verification environment.

The Canon India Design Centre chose the Questa advanced verification platform, combined with the OVM, to ensure the highest level of modularity, productivity and reuse for the verification of Canon India’s complex and highly compute-intensive integrated circuit (IC) designs. In particular, the Canon India Design Centre verification team used SystemVerilog with OVM for verifying multi-layered communication IP.

“The OVM defines the concept of ‘object oriented’ for verification environment in a systematic way,” said Sunil Kashide, Verification head at the Canon India Design Centre. “We were able to define and build the verification architecture much more robust and modular. Mentor India has given extensive support in understanding and exercising the different concepts. With OVM, we could reduce the overall timeline by bringing parallelism into execution.”

“Mentor Graphics’ team has provided us extended support during the evaluation phase,” said Dhanaji Kamble, Design Centre head. “We could successfully build the domain expertise and boost team confidence for the next-generation verification methodology.”

“The OVM was developed to deliver ready-to-use, reusable, and scalable testbench components within a proven, repeatable methodology,” said John Lenyo, general manager of Mentor’s Functional Verification division. “The combination of industry-leading SystemVerilog support and OVM-specific debug capabilities in the Questa functional verification environment has helped customers like Canon India quickly get successful results in real projects.”

About the Open Verification Methodology (OVM)

The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open and includes a robust class library and source code that is available for download. Visit for more information.

About Canon India

Canon India Private Limited, India’s No. 1 Complete Digital Imaging Company, started the software development centre ISDC (India Software Development Centre) in 1999. The ISDC is comprised of multiple divisions, namely SDC (Software Development Centre), CoE (Centre of Excellence) and Design Centre. SDC and CoE are located at Noida and Design Centre is located at Bangalore.

The Design Centre at Bangalore started in 2008 with a vision to focus on VLSI/ASIC Design and Firmware/Software development. The key areas of focus for the ASIC Design group are: IP development, Verification IP Development, SoC (System on Chip) architecture and development, Post-silicon Validation, and FPGA prototyping. The group is well skilled to tape-out the multi-million gate count SoC with 45nm and 65nm technology. The verification team is highly skilled to work in state-of-the-art verification methodologies.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070-7777. World Wide Web site:

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