fish fry
Subscribe Now

The Future is Verified

Looking Forward to DVCon 2017 with Dennis Brophy

Design verification is front and center in this week’s episode of Fish Fry. Dennis Brophy, General Chair of DVCon, gives us a special sneak peek into the Design Verification Conference and Expo taking place next week in San Jose, California. Please join me as Dennis and I explore the variety of tutorials, keynotes, and sessions you will find at DVCon. We also discuss how to learn about advanced verification methodologies and techniques, how to apply formal methods to the art of verification, and how to achieve the next level of design verification productivity. Then, for something completely different, our Kickstarter Corner highlights a new campaign launched by a team at MIT Media Lab that transforms air pollutants into unique art supplies. 

  

 

Download this episode (right click and save)

Links for February 24, 2017

More information about the 2017 Design Verification Conference and Expo

Accellera Day Opens DVCon U.S. on Monday, February 27 with Three Timely Tutorials

Kickstarter Corner: More information about AIR-INK

Leave a Reply

featured blogs
Dec 5, 2023
Introduction PCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone diversified changes, spread across transaction, data link and physical layers. The l...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

The Future of Intelligent Devices is Here
Sponsored by Alif Semiconductor
In this episode of Chalk Talk, Amelia Dalton and Henrik Flodell from Alif Semiconductor explore the what, where, and how of Alif’s Ensemble 32-bit microcontrollers and fusion processors. They examine the autonomous intelligent power management, high on-chip integration and isolated security subsystem aspects of these 32-bit microcontrollers and fusion processors, the role that scalability plays in this processor family, and how you can utilize them for your next embedded design.
Aug 9, 2023
14,283 views