EEJournal

fish fry
Subscribe Now
February 5, 2016

Safety (and Security) First

Embedded Software, TÜV Certification, and 64 bits
by Amelia Dalton

In this week’s Fish Fry, we’re taking on safety, security, and the embedded design software in between. Michael May (Express Logic) and I start things off with an in-depth discussion about the ongoing design-in battle between 32 and 64 bit processors and where ThreadX RTOS fits into the embedded ecosystem. Keeping with this week’s embedded software theme, I also chat with Jim McElroy (LDRA) about what we need to do when our designs must adhere to a security-critical standard, why TÜV Certification is so important, and what it’s like to capitan a whale watching boat.

 

 

Download this episode (right click and save)

Links for February 5, 2016

More information about Express Logic

More information about LDRA

LDRA Extends TÜV Certification of Compliance Tools, Further Solidifying Leadership Role in Safety and Security Markets

New Episode of Chalk Talk: Cadence Tensilica Vision P5

Leave a Reply

featured blogs
Building Verification Infrastructure for Complex PCIe Verification
Dec 5, 2023
Introduction PCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone diversified changes, spread across transaction, data link and physical layers. The l...
More from Cadence...
Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
More from Synopsys...
A Haunting World Underwater
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
More from Max's Cool Beans...

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

High-Voltage Isolation for Robust and Reliable System Operation
Sponsored by Mouser Electronics and Texas Instruments
In this episode of Chalk Talk, Amelia Dalton and Luke Trowbridge from Texas Instruments examine the benefits of isolation in high voltage systems. They also explore the benefits of TI’s integrated transformer technology and how TI’s high voltage isolations can help you streamline your design process, reduce your bill of materials, and ensure reliable and robust system operation.
Click here for more information about Texas Instruments ISOW774x/ISOW774x-Q1 Quad-Ch Digital Isolators
Apr 27, 2023
24,878 views