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What You Call EDA, I Call IP

EDA Past, Present, and Future with Lucio Lanza

He’s toiled at this project for years – dreamt about it, laid awake at night thinking about it, and even built a lab in his basement to test it. Eventually he brought in friends (from work mostly) to fill in the missing pieces, and before he knew it they really had something. We all know this story. It has played out time and time again. It’s the story of the startup, and today’s Fish Fry celebrates the men and women who work every day with innovation in their hearts and minds. My distinguished guest is Lucio Lanza, an EDA mentor, venture capitalist, and believer in startup innovation. Lucio is here to explain why funding startups is so crucial in today’s EE ecosystem and where he thinks EDA is headed in the future. Also this week, we check out a brand new way to get that semiconductor quote you’ve been looking for without giving you a headache or breaking your fax machine.

 

 

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Links for December 19, 2014

EDA Industry to Recognize Dr. Lucio Lanza With the Phil Kaufman Award at ICCAD 2014

New Episode of On the Scene: Almost-Instant Semi Quotes with eSilicon

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EdgeQ Creates Big Connections with a Small Chip

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Find out how EdgeQ delivered the world’s first 5G base station on a chip using Cadence’s logic simulation, digital implementation, timing and power signoff, synthesis, and physical verification signoff tools.

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featured chalk talk

"Scalable Power Delivery" for High-Performance ASICs, SoCs, and xPUs

Sponsored by Infineon

Today’s AI and Networking applications are driving an exponential increase in compute power. When it comes to scaling power for these kinds of applications with next generation chipsets, we need to keep in mind package size constraints, dynamic current balancing, and output capacitance. In this episode of Chalk Talk, Mark Rodrigues from Infineon joins Amelia Dalton to discuss the system design challenges with increasing power density for next generation chipsets, the benefits that phase paralleling brings to the table, and why Infineon’s best in class transient performance with XDP architecture and Trans Inductor Voltage Regulator can help power  your next high performance ASIC, SoC or xPU design.

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