Over the FR4 and Through the Woods

To Grandma's PCB We Go

by Amelia Dalton

This week’s Fish Fry is all about your next PCB design. From power integrity to mixed-signal place and route, from Gerber files to schematics, from output pins over the FR4 and through the vias, to grandma’s house we go. My first guest this week is Greg Lebsack from Tanner EDA, and we discuss why you want a digital place and route tool, integrating ye ol’ analog into your next design, and what Tanner EDA brings to the mixed-signal party. Next up, we bring in Hemant Shah from Cadence Design Systems to chat about one of the biggest pain points of PCB design: the hand off to manufacturing. Hemant and I investigate a rapidly expanding industry consortium that is hoping to change all of that awful file hand off once and for all.

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Links for November 21, 2014

More information about Tanner EDA

Tanner EDA Completes Analog/Mixed-signal Flow with Digital Place and Route in Release v16.1 of HiPer Silicon Design Suite

More information about the IPC 2581 Consortium

New Episode of Chalk Talk – The Vault

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

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Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Shift Left Block/Chip Design with Calibre

Sponsored by Siemens Digital Industries Software

In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.

Click here for more information about Shift left solutions for IC design stage verification

Jun 18, 2024

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Over the FR4 and Through the Woods

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