fish fry
Subscribe Now

Hardware-Assisted Electronic Pesticide

Findin' Them Buggers Fast

Maybe it’s an itch that just won’t go away. Maybe it’s a daydream buster – Aw dang, I didn’t think of that. Or, maybe it’s a recurring nightmare that runs you ragged each and every night. Yep, we’re talking about hardware-assisted verification. It ain’t easy and nobody ever said it was going to be. In this week’s Fish Fry my guest is Frank Schirrmeister from Cadence Design Systems. We chat about why hardware-assisted verification is on everybody’s mind these days, and what we can do to make our verification lives a whole bunch easier.

We’ll also tell you how you can join the IoT party with Atmel’s new SAM D20 Cortex M0+ family, and our giveaway this week is an Atmel AVR Butterfly (courtesy of Newark element14).

 

Enter to win an Atmel AVR Butterfly courtesy of Newark element14. 


Listen to this episode

Download this episode (right click and save)


Links for September 13, 2013

Cadence Launches Palladium XP II Verification Platform and Enhanced System Development Suite

New Episode of Chalk Talk – Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

More Information about the Atmel AVR Butterfly

Leave a Reply

featured blogs
Nov 12, 2024
The release of Matter 1.4 brings feature updates like long idle time, Matter-certified HRAP devices, improved ecosystem support, and new Matter device types....
Nov 7, 2024
I don't know about you, but I would LOVE to build one of those rock, paper, scissors-playing robots....

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
35,777 views