fish fry
Subscribe Now

DesignCon Take 2

Floating Point for FPGAs and TI’s Signal Integrity Solutions

In part two of my DesignCon 2012 coverage, I chat with Mike Parker (Altera) about FPGAs doing floating point and where he feels we are are headed in this realm. I also chat with Sanjay Gajendra (Texas Instruments) about how TI is aiming to make your multi-gigabit SerDes signal integrity issues a whole bunch easier. Also this week, I check out why the “app economy” has become a big deal in the United States and how a 9 year old girl is trumping this week’s mainstream scientific achievements.

I have another very cool MAX V CPLD Development kit (courtesy of Altera) to give away this week, but you’ll have to listen to find out how to win.

 

Watch Previous Fish Frys

Fish Fry Links – February 10, 2012

Taking Advantage of Advances in FPGA Floating-Point IP Whitepaper

More Information about Texas Instruments’ Signal Conditioning

More Information about the “App Economy”

Best Buy SuperBowl Commercial Features App Developers

9 Year Old Student Discovers New Molecule

More information about Altera’s MAX V CPLD Development Kit

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

John Bruggeman, Former CMO – Cadence Design Systems

Darrin Billerbeck, CEO – Lattice Semiconductor

Lauro Rizzatti, Vice President of Marketing, EVE

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Kapil Shankar, CEO – SiliconBlue

Andy Pease, CEO – QuickLogic

Rajeev Madhavan, CEO – Magma 

Paul Kocher, President – Cryptography Research Inc.


Leave a Reply

featured blogs
Feb 24, 2020
The MSGEQ7 8-pin dual in-line (DIL) integrated circuit accepts an audio stream as input and splits it into seven different "frequency buckets."...
Feb 24, 2020
Most people, when they think about numbers, mathematics or science, are thinking about precision – getting exact answers. However, I have observed that, in many fields, this may not be a clear perception. For example, in accounting it is expected that a balance sheet wi...
Feb 21, 2020
DesignCon 2020 wrapped-up a few weeks ago. DesignCon, which celebrated its 25th anniversary in January, is an important conference/exhibition for Samtec. It'€™s an opportunity to present our new signal integrity optimized, high-performance interconnect and technology s...
Feb 21, 2020
[From the last episode: We looked at how the '€œconcurrency'€ of multiple threads on a single CPU was actually illusory '€“ but still useful.] Last time we talked about concurrency, by which we mean multiple threads or programs being executed at the same time. Which, a...

Featured Video

Industry’s First USB 3.2 Gen 2x2 Interoperability Demo -- Synopsys & ASMedia

Sponsored by Synopsys

Blazingly fast USB 3.2 Gen 2x2 are ready for your SoC. In this video, you’ll see Synopsys and ASMedia demonstrate the throughput available with Synopsys DesignWare USB 3.2 IP.

Learn more about Synopsys USB 3.2