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DesignCon Take 2

Floating Point for FPGAs and TI’s Signal Integrity Solutions

In part two of my DesignCon 2012 coverage, I chat with Mike Parker (Altera) about FPGAs doing floating point and where he feels we are are headed in this realm. I also chat with Sanjay Gajendra (Texas Instruments) about how TI is aiming to make your multi-gigabit SerDes signal integrity issues a whole bunch easier. Also this week, I check out why the “app economy” has become a big deal in the United States and how a 9 year old girl is trumping this week’s mainstream scientific achievements.

I have another very cool MAX V CPLD Development kit (courtesy of Altera) to give away this week, but you’ll have to listen to find out how to win.

 

Watch Previous Fish Frys

Fish Fry Links – February 10, 2012

Taking Advantage of Advances in FPGA Floating-Point IP Whitepaper

More Information about Texas Instruments’ Signal Conditioning

More Information about the “App Economy”

Best Buy SuperBowl Commercial Features App Developers

9 Year Old Student Discovers New Molecule

More information about Altera’s MAX V CPLD Development Kit

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

John Bruggeman, Former CMO – Cadence Design Systems

Darrin Billerbeck, CEO – Lattice Semiconductor

Lauro Rizzatti, Vice President of Marketing, EVE

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Kapil Shankar, CEO – SiliconBlue

Andy Pease, CEO – QuickLogic

Rajeev Madhavan, CEO – Magma 

Paul Kocher, President – Cryptography Research Inc.


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