EEJournal

fish fry
Subscribe Now
March 4, 2011

Old Is The new New

A Hardware Design Language for All, Apps for Your O-Scopes and Chip-Scale Wireless Networks
by Amelia Dalton

In my Fish Fry this week, I investigate the re-birth of an old system language coming back into style, delve into the world of cloud-based applications for oscilloscope users and check out a cool new way to connect the pieces on your board using a nano-wireless router.  Also this week, I reveal a seriously cool nerdy giveaway and offer up a surprise award to next week’s winner.

If you like the idea of this new series, be sure to drop a comment in the box below. I appreciate all of your comments so far, and we will be working to enhance the Fish Fry each week – as long as you’re watching.

 

Watch Previous Fish Frys

Fish Fry Links – April 1, 2011

APL

Analog Evaluation Board – the MCP1640 Single Cell Boost Converter for Energizer MAX Alkaline

Leave a Reply

featured blogs
Training Insights: Cadence Cerebrus Webinar Recording Now Available!
Dec 7, 2023
Semiconductor chips must be designed faster, smaller, and smarter'”with less manual work, more automation, and faster production. The Training Webinar 'Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have' was recently hosted with me, Krishna Atreya, Princ...
More from Cadence...
The Importance of Memory Architecture for AI SoCs
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
More from Synopsys...
A Haunting World Underwater
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
More from Max's Cool Beans...

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Enable Sustainable Enterprises of the Future
Sponsored by Mouser Electronics and Analog Devices
Did you know that buildings are responsible for 40% of global energy consumption and 33% of greenhouse gas emissions? One way we can help both modernize and increase sustainability in our buildings is by adding 10BASE-T1L to our building controllers. In this episode of Chalk Talk, Amelia Dalton chats with Salem Gharbi from Analog Devices about how we can enable sustainable enterprises with ethernet connected building controllers. They examine the10BASE-T1L flexible design solutions that Analog Devices offers, how exiting?building infrastructure can take advantage of 10BASE-T1L and how you can get started on your next sustainable enterprise journey.
More information about Analog Devices Inc. ADIN1100 10BASE-T1L Ethernet PHY
Dec 20, 2022
41,445 views