EEJournal

fish fry
Subscribe Now
March 4, 2011

Portion Control: Prototypes, Processors and Printed Food

Fish Fry - March 4, 2011
by Amelia Dalton

In my Fish Fry this week, I dive into the wild world of FPGA prototyping and offer up an elixir that might just solve all of our prototyping problems. I also investigate a unique new trend that brings processors and FPGA fabric together in off-the-shelf embedded systems and check out a new invention that could bring the Star Trek food replicator to life.  Also this week, I announce the winner of last week’s nerdy giveaway and offer up a new one to chew on. 

If you like the idea of this new series, be sure to drop a comment in the box below. I appreciate all of your comments so far, and we will be working to enhance the Fish Fry each week – as long as you’re watching.


 

Watch Previous Fish Frys

Fish Fry Links – March 4, 2011

Synopsys/Xilinx FPGA Prototyping Manual

FPMM Community

Jim Turley’s Article: Xilinx Zynq Zigs, Zags and Zooms

HSI iSuppli iPad 2 Teardown

3D Printed Food

Microchip Explorer16 Development Board

Leave a Reply

featured blogs
Training Insights: Cadence Cerebrus Webinar Recording Now Available!
Dec 7, 2023
Semiconductor chips must be designed faster, smaller, and smarter'”with less manual work, more automation, and faster production. The Training Webinar 'Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have' was recently hosted with me, Krishna Atreya, Princ...
More from Cadence...
The Importance of Memory Architecture for AI SoCs
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
More from Synopsys...
A Haunting World Underwater
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
More from Max's Cool Beans...

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Universal Verification Methodology Coverage for Bluespec RISC-V Cores

Sponsored by Synopsys

This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and a RISC-V processor core from Bluespec.

Click to read more

featured chalk talk

Achieving High Power Density with IGBT and SiC Power Modules
Sponsored by Mouser Electronics and Infineon
Recent trends in the inverter market have made high power density, scalability, and ease of assembly more important than ever before. In this episode of Chalk Talk, Amelia Dalton and Abraham Markose from Infineon examine how Easy & Econo power modules from Infineon can help solve common inverter design requirements. They explore the benefits and construction of these modules and how you can take advantage of them in your next design.
Click here for more information about Infineon Technologies EconoDUAL™ 3 IGBT Modules
May 19, 2023
23,120 views