editor's blog
Subscribe Now

What Does a 5nm Transistor Look Like? I

Synopsys and Imec recently announced that they’d be collaborating on TCAD activities for the 5nm node.

Yup. 5nm. You can count ‘em on one hand.

We get to see lots of ideas on how things might happen in the future, but once you start defining a specific node, well, it’s time to get specific about what that node’s gonna look like. So I had a quick conversation with Imec’s Aaron Thean on what the notable changes would be at that node.

Because, unlike the old days, when each new node made things smaller, perhaps adding a new technique or tweak here and there to help with the shrinkage, these days it seems that, every couple nodes, something big has to change.

Like going from planar transistors to FinFETs. Or introducing double-patterning. And for all that work, it only buys you a couple nodes – you don’t get to reap the reward for the next 20 years. No time to relax; once you’ve gotten the latest major change completed, time to plan the next one.

While, presumably, each node has its share of evolutionary refinements from the prior node, I wanted to zero in on the big changes. One potentially big change that perhaps isn’t so big after all is EUV, but at 5nm, they’ll still need double-patterning – even with EUV. So hopefully EUV won’t be new at that point – what a drag to have a new litho technology that can free us from double-patterning, only to have it delayed to the point where it also needs double-patterning. Doh!

So that’s not the big one. I hope. The big change is likely to be transistor orientation – again. He sees FinFETs living on down through the 7nm node, but below that, routing challenges are finally going to be too great. At 7 nm, the channel will likely be nanowires instead of a fin, but it will still be horizontal. At the 5nm node, they’re looking at flipping that nanowire up to make it vertical.

In other words, they’ll grow a “forest” of these – well, what I call “pins” – and create transistors out of them. I’ve referred to these in the past as “pinFETs.” Imec refers to them as “VFETs.”

By standing the channel up, you obviously reduce the transistor footprint dramatically. This frees up more routing room. But there’s also another big change: rather than the channel being contacted on the left and right, it’s now contacted on the top and bottom. That messes up the old convenient front-end and back-end distinction. Instead of all the interconnect going on top of the transistors, now the channel will reside between two layers of interconnect. So some of the interconnect will go down before the transistor is built.

They’ve done some trial layouts and have found a rather significant reduction in area by using such a transistor, as exemplified by the NAND gate below.

5-nm_image.png

Image courtesy Imec

And when will all of this be coming to a fab near you? He sees 7nm risk starts in the 2018 timeframe; 5nm will lag that by only a couple years: 2020.

Oh, and in case you’re reserving time in your calendar, 3-4nm risk starts are anticipated in the 2022-24 range.

I can hardly wait.

Leave a Reply

featured blogs
Mar 28, 2024
The difference between Olympic glory and missing out on the podium is often measured in mere fractions of a second, highlighting the pivotal role of timing in sports. But what's the chronometric secret to those photo finishes and record-breaking feats? In this comprehens...
Mar 26, 2024
Learn how GPU acceleration impacts digital chip design implementation, expanding beyond chip simulation to fulfill compute demands of the RTL-to-GDSII process.The post Can GPUs Accelerate Digital Design Implementation? appeared first on Chip Design....
Mar 21, 2024
The awesome thing about these machines is that you are limited only by your imagination, and I've got a GREAT imagination....

featured video

We are Altera. We are for the innovators.

Sponsored by Intel

Today we embark on an exciting journey as we transition to Altera, an Intel Company. In a world of endless opportunities and challenges, we are here to provide the flexibility needed by our ecosystem of customers and partners to pioneer and accelerate innovation. As we leap into the future, we are committed to providing easy-to-design and deploy leadership programmable solutions to innovators to unlock extraordinary possibilities for everyone on the planet.

To learn more about Altera visit: http://intel.com/altera

featured chalk talk

Accessing AWS IoT Services Securely over LTE-M
Developing a connected IoT design from scratch can be a complicated endeavor. In this episode of Chalk Talk, Amelia Dalton, Harald Kröll from u-blox, Lucio Di Jasio from AWS, and Rob Reynolds from SparkFun Electronics examine the details of the AWS IoT ExpressLink SARA-R5 starter kit. They explore the common IoT development design challenges that AWS IoT ExpressLink SARA-R5 starter kit is looking to solve and how you can get started using this kit in your next connected IoT design.
Oct 26, 2023
19,905 views