I’ve been following alternative and persistent memory technologies for 40 years. Back in the 1980s, all we had for semiconductor memory was SRAM, DRAM, EPROM, and {non-Flash) EEPROM. During the late 1980s, when I first transitioned from working as an engineer to an editor for an electronics publication, I wrote about nascent, low-capacity, persistent memories offered by two companies located in Colorado Springs: ferroelectric memory (FRAM) made by Ramtron, and SONOS Flash memory with an SRAM shadow memory array from Simtek. Ramtron’s gone, but FRAM is still kicking, and Cypress bought Simtek in 2008. (Infineon bought Cypress in 2020.)
Toshiba started making Flash memory in 1987 and the technology really caught on in the 1990s. Today, Flash EEPROM is in wide use for on-board and on-chip code and data storage, while DRAM has evolved into SDRAM, which simplified some things related to RAM storage – such as RAS/CAS timing and refresh cycles – and vastly complicated others, like requiring matched-length, high-speed traces on circuit boards. For the last decade or so, newer alternative and persistent memory technologies have been emerging, including updated FRAM, magnetic RAM (MRAM), resistive memory (ReRAM), and phase-change memory (PCM). All these technologies are vying to go mainstream in the role of persistent storage class memory (SCM) – the long-sought Holy Grail for computer memory.
In January, the Storage Networking Industry Association (SNIA) sponsored an alternative memory technology Webinar. The presenters were my two favorite memory technology experts: Tom Coughlin (Coughlin Associates) and Jim Handy (Objective Analysis). These two experts provided an up-to-the-minute status report on alternative memory development, and they delivered some fresh, new insights about the use of these alternative memories for embedded and for more classical computer memory applications.
Coughlin started the presentation by discussing the types of memory used in on-chip applications, specifically microcontrollers. These ubiquitous devices typically employ NOR Flash memory to store code and unchanging data, and they incorporate a relatively small block of on-chip SRAM to store volatile data. According to Coughlin, NOR Flash memory cells stopped scaling at 28nm because that’s the last planar FET process node. FinFET circuitry has no NOR Flash cell. Consequently, for microcontrollers to make use of smaller semiconductor manufacturing nodes, chipmakers will need to use one of the alternative forms of nonvolatile memory for storing code.
There are three possibilities here, according to Coughlin. First, semiconductor vendors could combine FinFET logic circuits with planar NOR Flash on the same chip. This solution is economically nonviable, especially for relatively low-cost parts like microcontrollers, because the whole chip will travel through the entire advanced semiconductor process, which will cost significantly more than fabricating the chip using older process nodes.
The second alternative is to use external Flash storage for code. This solution also has severe disadvantages because it implements a 2-chip solution, which is more costly, and because it burdens the microcontroller’s package design with extra pins that will be needed to communicate with the external memory. Note that most FPGAs routinely use external serial Flash memories for configuration storage, but FPGAs have hundreds or thousands of I/O pins. They cost a lot more than microcontrollers and are used to build larger, more expensive systems. So the added disadvantages of an extra configuration EEPROM in FPGA-based systems isn’t nearly as burdensome.
In addition, microcontroller-based systems that might take this approach and use external serial Flash memory would need to move code from the external Flash memory to on-chip SRAM to achieve acceptable execution performance, which would require additional on-chip SRAM capacity. This, too, drives the microcontroller chip’s cost up, doubly so because on-chip SRAM isn’t scaling as fast as logic in FinFET processes, as shown in the graph below. Consequently, this alternative is both more expensive and technically inferior from a performance perspective.
SRAM cells are not scaling as fast as logic in the more advanced FinFET process nodes. Image credit: Objective Analysis
That leaves the third alternative, which is to use an entirely different on-chip storage technology. Candidates for alternative nonvolatile memory storage include most of the memory technologies listed above: FRAM, MRAM, and ReRAM, and the first microcontrollers with these types of memory are already starting to appear. NXP and TSMC announced a collaboration to develop MRAM-based microcontrollers for the automotive market in 2023. Texas Instruments’ MSP430FR57xx family employs as much as 16 Kbytes of FRAM for its on-chip, non-volatile storage. Renesas discussed an experimental microcontroller with 10.8 Mbits of on-chip MRAM for nonvolatile storage at ISSCC last year. Also in 2024, Nuvoton announced the M2L31 microcontroller based on Arm’s Cortex-M23 processor core, which integrates as much as 512 Kbytes of ReRAM for on-chip, nonvolatile storage. (See “Nuvoton’s One-Arm M2L31 Microcontroller Uses ReRAM (Memristors) for On-Chip, Non-Volatile Storage.”) These early experiments with alternative types of nonvolatile, on-chip memory are harbingers of things to come. With foundries like TSMC offering process adders like MRAM and ReRAM to its ASIC and ASSP customers, I expect to see more such devices appear in the future.
At this point in the presentation, Jim Handy took over to discuss these new nonvolatile memory technologies in more depth. Handy took a hard look at the key foundational memory process technologies that have supported semiconductor development since the 1970s. NAND Flash memory, the mainstay of nonvolatile storage, hit a brick wall with respect to scaling at 15nm. Consequently, NAND Flash chipmakers were forced to go vertical by developing the 3D variant of NAND Flash memory. Since 3D NAND chips started to appear in 2007 (once more, Toshiba led the way), the layers have been piling up. Last year, SK hynix announced a 3D NAND Flash memory chip with an astounding 321 layers. However, Handy pointed out that even with 3D NAND memory cells, NAND Flash chips stop scaling around 10nm. Meanwhile, DRAM cells have essentially been 3D cells since the 1990s when DRAM makers introduced trench capacitors, so these cells are similarly limited with respect to process shrinks.
These limits in multiple dimensions are forcing chipmakers to consider alternative memory technologies, which do hold out the promise of future device scaling. However, the early attempts at moving these memory technologies into the mainstream have not gone well. Intel and Micron jointly developed a PCM technology, which Intel called Optane and Micron called 3D XPoint. Micron ceased 3D XPoint development in 2021, and Intel discontinued Optane in 2022. The Intel/Micron PCM technology attempt failed because it was too expensive to make the devices when compared to NAND Flash memory and DRAM. However, says Handy, because these memory technologies, including PCM, can be layered on top of semiconductor logic, they may become economically viable as chips continue to shrink, because the memory array, constructed on top of the logic circuits, does not increase the chip’s overall size and therefore keeps manufacturing costs down.
Handy pointed out that all these alternative, nonvolatile memory technologies share certain attractive attributes. First, they’re radiation tolerant, which is good for certain uses such as space and military applications. There’s a lot of radiation in space, and there’s a premium for memories that won’t lose bits in high-radiation environments. In addition, all these alternative nonvolatile memory technologies write much faster than Flash, and they’re byte-writable, which makes two more advantages for which there’s a premium because system performance improves when you don’t need to erase and write entire pages; all you need to do is update a byte or two. Handy says these technologies are all scalable well beyond 28nm, so he expects that the cost structure is only going to improve. On the negative side of the equation, these new memory technologies require the use of innovative materials, “and that’s actually just a deal killer,” said Handy.
Towards the end of the presentation, Handy discussed a “very rough” timeline for the introduction of these new memories for mainstream use. His projected timeline for the next 20 years appears in the graphic below.
Jim Handy’s timelines for the introduction of alternative memory technologies into mainstream use. Image credit: Coughlin Associates and Objective Design
MRAM is already used in embedded applications such as hearing aids and AR glasses. Nevertheless, Handy believes it will take another decade or so before these alternative memory technologies supplant Flash memory and SRAM in embedded applications, because the pace of development for microcontrollers just isn’t very fast. The economics isn’t driving microcontroller scaling.
Handy expects the cost structures of external NAND Flash chips and SDRAMs will delay the use of alternative memory technologies in standalone memory chips, relative to their use in embedded applications. However, when the transition starts, Handy predicts that it will occur more quickly, so that the changeover will be complete shortly after the same transition has occurred for embedded applications. Handy expects the same transition will happen for memory chiplets, but with even more initial delay due to the industry’s relatively slow pace in adopting chiplets overall. Again, the economics do not yet compel the use of chiplets, except for systems targeting the pinnacle of performance.
In conjunction with this presentation, Coughlin and Handy have written a 300-page report covering new memory technologies in far more detail. It’s titled “A Deep Look at New Memories.” If you’re interested in the report, it’s available for purchase here. You can also listen to the SNIA Webinar on new memory technologies by clicking here.
