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Mentor Xpedition Raises PCB Validation Ante

As electronic system design has evolved, the practice of designing in specialized silos has broken down. Challenges such as signal integrity for multi-gigabit signals has forced co-design that spans every level of design from system to board to package to IC. Other issues, including thermal, power, RF, EM, and many more, have exacerbated this effect. As much as we wish we could just design our PCB in isolation, the cold hard tendrils of modern reality snake their way into our project and ensnare us at every turn.

Similarly, the idea of stand-alone point design tools is rapidly becoming a distant memory. PCB layout tools have expanded to become multi-board system planning, design, and verification environments, and the once-clean lines between design tools and tasks has blurred themselves practically out of existence. In that vein, the major suppliers of EDA tools for PCB design have all leveled-up their talking points and are now focusing on enabling first-time success in board-based system design.

Mentor (now a Siemens company) has long been the market leader in EDA for PCB. For the past several years, they’ve focused their enhancements and announcements on addressing challenges faced by today’s system designers – 3D board design, rigid-flex, high-density packaging, multi-board design – as well as bringing verification into the picture with an integrated, unified analysis environment and a new vibration analysis capability. This year, the company is focusing on “right the first time” design of board-based systems by working to move verification capabilities to earlier in the design cycle, all aimed at the goal of reducing or eliminating PCB re-spins.

Citing a recent study by Lifecycle Insights that claims that the average PCB design project requires 2.9 respins, Mentor is taking aim at the common causes of design errors and creating capabilities to allow designers to “shift left” by bringing critical checks and analysis earlier in the process – hopefully catching problems when they are authored, rather than after bad boards come back from the fab. Certainly this is a noble goal, but it’s also quite an ambitious undertaking, considering the complexity and breadth of analysis capabilities required.

While early validation and verification are becoming more mainstream, most PCB design teams still rely on building and debugging by iterating prototype boards. Increasingly, though, the cost, complexity, and iteration cycle time for turning those boards around has increased. Further, the practice of cobbling together functional prototypes using collections of development boards and modules has become less practical due to signal integrity issues. That has put additional pressure on the prototype PCB spin as a functional verification platform.

Mentor is working to push the analysis and verification steps back into the schematic and layout stages of design, with the intent of catching design errors when they occur, rather than in the lab, with a physical PCB prototype. The company claims that, in addition to reducing respins, this speeds up the process by avoiding the need to bring in specialists (such as signal and power integrity experts), who can often become bottlenecks in the project. By building in, for example, schematic checking, Mentor says that they can identify the most common schematic integrity errors before layout starts. The new version of Mentor’s Xpedition includes integrated automated schematic verification that “performs exhaustive, rapid, power- and technology-aware tests of all nets in the schematic, analyzes single and multi- board designs, and leverages over 150 voltage-aware rules.”

This release of Xpedition also features a new integrated testability analysis capability that Identifies test-point requirements in schematic, passes them to layout, and confirms testability coverage within the resulting layout. It also creates optimized outputs for test machines. The up-front testability analysis is designed to replace the traditional post-design process testability analysis. Mentor says the tool will accelerate manufacturing handoff by identifying process defects, reduce errors associated with insufficient test coverage, and improve development of more efficient and cost-effective test processes. Moving this design-for-test forward in the design cycle again avoids a type of respin that typically occurs very late in the process, where the board is functionally correct and most other issues such as thermal and EMI have been controlled, and then somebody says, “Oh, dang! We can’t quite test these things properly.”

With these new additions, Xpedition’s validation and verification capabilities are quite robust, including multi-board schematic validation, analog / mixed-signal analysis, design-for-test-constraint definition, and signal- and power-integrity design exploration at the schematic level.  Moving on to the layout phase, Mentor supports signal- and power-integrity validation, thermal analysis, EMI validation, and vibration- and acceleration-analysis. Finally, for post-layout signoff, they offer design-for-manufacturing (DFM) validation as well as final electrical rule checking. Taken together, these analysis and verification steps promise to make a sharp cut in the number of respins required for the typical team. Or, at least – for the typical team with the discipline to use all of those facilities.

The integration between the various design and analysis tools, as well as real-time sharing of databases and libraries, allows many of these checks to happen interactively as the design work is being done. It’s hard to overstate the value of seeing an error as you are making it, versus finding it even a day or so later when your mind is no longer in the context. Engineers, like pets, are best trained if you catch us in the act, rather than after the fact.

Interestingly, in some teams, the experts in various disciplines sometimes feel threatened by the deployment of new checkers designed for “non-expert” designers. For the SI expert, for example, there is considerable satisfaction in the process of looking over a design and offering a “tsk tsk” for each of the issues uncovered in the non-SI-expert’s design. More upfront checking will certainly result in fewer job-satisfaction “saves” for the various experts, but the higher rate of on-time project completion should more than soothe any injured egos in your team’s specialists.

It’s good to see that Mentor continues to invest and advance in critical system- and PCB-design technology in the wake of the acquisition by Siemens. Often, key value and technology are squandered during acquisitions, and it will be interesting to watch how the Mentor/Siemens technology and products evolve in the coming years.

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