Xilinx announced the Spartan-6 FPGA family in 2009, based on a 45 nm IC process technology. Over time, the Spartan-6 LX family grew to encompass FPGAs with 3.84K to 147K logic cells, as many as 576 I/O pins, 180 DSP slices, and 268 18-Kbit Block RAMs. Spartan-6 LXT FPGAs provide the same range of logic resources as the Spartan-6 LX family members, while providing as many as eight GTP transceivers, each capable of operating at 3.125 Gbps, and one PCI Express end point, capable of operating at 2.5 Gbps. (Note: That’s the PCIe 1.0 data rate per lane.)
Because these FPGAs are 13 years old, and because there’s now an ongoing shortage of older parts like the Spartan-6 family, you may be considering a design migration to newer devices. At the 50,000-foot level, the Xilinx Spartan-7 FPGA family, announced in 2015, might seem like an obvious migration path. However, the jump from Spartan-6 to Spartan-7 FPGAs is not as straightforward as it might seem.
Adam Taylor, an expert who’s had many years of engineering design experience with Xilinx FPGAs (and FPGAs from other vendors as well), has written a 20-page White Paper titled “Migrating Spartan 6 Design to 7 Series & Beyond” to help you make a migration decision. You can download this free White Paper from his Web site. In this article, I’ll summarize Taylor’s observations and recommendations, to make it easier for you to decide whether or not to download his White Paper. (You should.)
Logic Cells, LUTs, Slices, and CLBs
The Spartan-6 and -7 FPGAs have similar 6-input LUTs with two associated flip flops. The architectures of the two FPGA families combine eight logic cells to create a slice. Each slice contains eight LUTs and 16 flip flops. The Spartan-6 and Spartan-7 FPGAs incorporate two slice types: Slice_M and Slice_L. The Slice_M LUT can act as a distributed memory or a shift register. The Slice_L cannot. Two slices combine to create a configurable logic block. Spartan-6 FPGAs also have a Slice_X, which is the most basic of the three slice configurations. If all of this seems overly complicated, that’s possibly because it is. Presumably, the different slice capabilities arose from limitations with the process technology that existed in 2009, and which no longer exist today.
Functions that were implemented using a Spartan-6 Slice_X can be easily accommodated within a Slice_L, and logic synthesis for Spartan-7 devices will automatically retarget Slice_X usage to Slice_L, which can improve your design’s performance. The key point to remember here is that it’s extremely unusual to explicitly call out a programmable-logic slice type when using RTL design techniques. That’s something that’s no longer done.
Block RAM (BRAM) architectures differ significantly between Spartan-6 and Spartan-7 FPGAs. Spartan-6 BRAMs are arranged as 18-Kbit blocks, which can be configured as two 9-Kbit blocks. Each Spartan-7 BRAM has a 36-Kbit capacity and can be configured as two 18-Kbit memories. For most applications, logic synthesis will automatically retarget the larger Spartan-7 BRAMs. However, if your design is organized with many smaller memories constructed from BRAMs, then you may need a larger Spartan-7 FPGA to support that many small memories.
To compensate, the Spartan-7 BRAM offers several significant improvements over the BRAM block used in Spartan-6 FPGAs. Spartan-7 BRAMs have built-in FIFO capabilities, easy facility for cascading BRAMs, and built-in ECC. These improvements can be quite handy. They’re all features that require additional programmable logic if implemented in a Spartan-6 FPGA.
Both Spartan-6 and Spartan-7 provide dedicated DSP Slices incorporating single-cycle, hardware multiplier/accumulators (MACs). Spartan-6 FPGAs employ a DSP48A1 slice with an 18×18-bit signed multiplier. Spartan-7 FPGAs employ a much more advanced DSP48E1 slice, which implements a 25×18-bit signed multiply. The DSP48E1 slice supports a SIMD (Single Instruction Multiple Data) mode, which allows increased throughput and can implement an ALU that performs any of ten different logic functions on the two input operands. The DSP48E1 slice also incorporates a built-in pattern detector and a 17-bit shift register. Again, all of these functions would require additional programmable logic if implemented in a Spartan-6 FPGA.
The Xilinx Vivado logic-synthesis engine should map designs using the older DSP48A1 slice to the newer DSP48E1 slice automatically. However, the DSP48E1 slice’s advanced functions, such as SIMD mode, won’t be mapped in automatically. Xilinx provides language templates in the Vivado editor to ease the use of these newer DSP features.
The Spartan-7 FPGA’s clocking architecture is significantly simpler than the clocking architecture implemented in Spartan-6 FPGAs. Clocking in a Spartan-6 FPGA employs several different buffer types including BUFG, BUFH, BUFIO2, and BUFPLL. Spartan-6 FPGAs also provide several other clocking resources including Digital Clock Managers (DCM) and Phase Locked Loops (PLL). If all of this seems overly complicated, that’s possibly because it is. Spartan-7 FPGAs implement a simpler clocking architecture that boosts performance significantly. While Xilinx design software will automatically migrate most Spartan-6 buffers, such as BUFH and BUFG, you will need to migrate buffers that are specific to Spartan-6, like BUFIO2, manually if you have directly instantiated them in your design.
Interfacing with high-performance external SDRAMs is critical for many FPGA-based designs. Both Spartan-6 and Spartan-7 FPGAs can interface directly with DDR, DDR2, DDR3, and LPDDR SDRAMs. However, Spartan-6 FPGAs incorporate as many as four hardened, integrated memory-controller blocks. Spartan-7 FPGAs implement the memory controller with a soft IP core and a hardened memory PHY. This design scheme gives Spartan-7 FPGAs more design flexibility. The Spartan-7 soft memory controller IP supports DDR2, DDR3, DDR3L, and LPDDR2 SDRAMs.
Transceivers and PCIe
Spartan-6 LXT FPGAs provide multi-gigabit GTP transceivers with a maximum speed of 3.125 Gbps. Spartan-7 FPGAs do not have high-speed transceivers. If your design requires high-speed transceivers, you cannot migrate the design to Spartan-7 FPGAs. You’ll need to use another member of the Xilinx 7 Series, including Artix-7, Kintex-7, or Virtex-7 FPGAs or the Zynq 7000 SoC family.
Possibly the biggest change between using Spartan-6 and Spartan-7 FPGAs will be the tool chain. For Spartan-6 devices, you use the Xilinx ISE, EDK, PlanAhead, and SDK tool chain. For Spartan-7 devices, you use the Xilinx Vivado and Vitis tool chains. According to Taylor, Vivado provides a quantum leap in capability compared to the older Xilinx ISE tool chain. Vivado allows you to work with pure RTL designs while leveraging a large IP Library using a tool called Vivado IP Integrator.
Taylor’s White Paper contains a wealth of additional information for engineers contemplating a migration from Spartan-6 to Spartan-7 FPGAs. It’s well worth your time to visit Taylor’s site, Adiuvo.com, and download the free White Paper.
Migration of instantiated modules such as BRAMs or DSP slices presents a challenge when moving your design from a Spartan-6 FPGA to a Spartan-7 FPGA. You might consider using a similar instantiation in your migrated design, but, if you want to create the most portable and flexible design, it is better to update your RTL description so that logic synthesis will infer the desired primitive. Just as you do not instantiate CLBs and define their logic function and connections, you should not be doing that with BRAMs, DSPs, and other functions.
Of course, removing the explicit instantiations from an existing design could trigger some design iterations to ensure that the synthesis tool correctly interprets the updated RTL description and uses the correct primitive. If you want to make sure that the synthesis tool infers specific primitives within Vivado, you can leverage the language templates supplied with the Vivado Editor. These language templates allow you to insert the coding structure needed to tell the synthesis tool how to map the desired primitive. Xilinx provides language templates in both VHDL and Verilog.
Now, go download Adam Taylor’s White Paper and let the real expert tell you how to do it.
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