Signal integrity (SI) is the bane of most system designers. Getting those signals to pass intact through all the twists and turns of your design can be a maddening experience. But modern signal integrity design and analysis is the enabling soul of most of today’s high-performance systems. Cadence’s Sigrity tools are an industry leader in the signal and power integrity game, and the recently announced 2018 release brings some welcome new capabilities to the table.
Signal integrity has absolutely no respect for organizational boundaries. Your company may have connector engineers, PCB designers, and package designers in completely different cubicles, but signal integrity problems have no qualms whatsoever about creeping into the crevices between those groups and causing major food fights. In order to accurately and completely model the SI picture, the entire signal chain, including packages, boards, and connectors, needs to be incorporated.
With the 2018 release, Cadence now allows the entire structure, including boards and connectors, to be modeled and optimized as one structure, via the new Cadence Sigrity 3D Workbench, which is included with the (get ready, this is a mouthful) “Sigrity PowerSI 3D EM Extraction Option” (helpfully abbreviated 3DEM). 3DEM allows mechanical structures such as cables and connectors to be merged with the PCB so that critical 3D signal paths that span the board and the connector can be optimized together. Any required updates to the PCB can then be back-annotated to PCB layout in Allegro.
3D Workbench targets both signal integrity (SI) and power integrity (PI) applications. It allows the import and merging of mechanical structures and associated electrical databases, and it also supports both full-featured and parametric 3D solid modeling. Support is built in for simulation of twisted pair wiring, backplanes plus connectors, connectors (HDMI, SATA, etc.), and SMA connector on PCB. The workflow with 3D Workbench replaces what is mostly a disjointed, point-tool-based flow in most companies, and it should significantly reduce time and errors normally caused by bridging gaps between disparate tools and processes.
SI and PI analysis are compute-intensive tasks, and there is always a compromise to be made between accuracy and performance. For real-world systems, the complexity of the problem is such that 3D analysis would be prohibitive. Cadence attacks this problem by splitting the analysis between components that require 3D for accuracy and those that can be adequately modeled with 2D analysis. 3D extraction is performed only when needed. Much faster 2D hybrid-solver extraction is then performed on the remaining structures before all the interconnect models are stitched back together. This allows full end-to-end channel analysis to be performed efficiently and accurately – even with signals crossing multiple boards.
Perhaps just as important in terms of finishing projects fast is the reduction of errors and the elimination of manual steps facilitated by the tight integration between tools. It is not uncommon for mistakes to be made in the translation of data between tools, or to have portions of signal paths double counted when stitching together models from multiple analysis steps and modes. By automating this flow, Cadence believes there will be a significant reduction in design cycle times as well as fewer errors and fewer costly respins.
Interestingly, by spanning the gap between tools and teams in their customer base, Cadence has had to span gaps of their own. This release combines tools and technology from multiple groups at Cadence, so the trend toward more vertical integration and more cross-domain and cross-discipline integration in design teams carries back into teams in EDA tool suppliers as well. We expect to see integration playing a continually increasing role in EDA flows as design challenges (such as SI and PI) that span multiple domains become more common, and as Moore’s Law slowly ramps down, allowing EDA developers more time to focus on design flow challenges rather than simply achieving the next semiconductor node.
The Sigrity 2018 release also brings in rigid-flex support for field solvers such as the Sigrity PowerSI® technology. Cadence says, “extraction from a single layout database provides accurate interconnect modeling of both rigid and meshed-ground flex cable zones.” As rigid-flex design becomes more common, the analysis of high-speed signals that pass from rigid PCB materials to flexible materials becomes a sticking point for SI analysis. This release allows rigid-flex PCB designs to use the same techniques as rigid designs, making analasys flows and processes more consistent and accurate.
There are several other goodies worth mentioning in the latest Sigrity release. For those modeling IC packaging, Cadence says that they have achieved a dramatic performance increase in this release, with a 3x performance speedup and a 75% reduction in memory consumption. XtractIM power integrity technology now addresses additional checking and usability requirements for front-to-back PCB design flows, with enhancements in hierarchical views and quick search, and also in filtering, comparison tree report, and tool tips. In Allegro PowerTree, there are HTML block-diagram enhancements and automated add-nodes-on-pads enhancements. And, finally, in Sigrity PowerDC, AC analysis technology has added additional checks that look at the weighted AC current and check for equal voltage. New batch-mode “projects” allow these two new workflows as well as others to be set up as a set of batch checks.
As the broad market for PCB design tools has become more commoditized, with inexpensive desktop solutions gaining increasing traction, suppliers like Cadence, who provide industrial-grade and enterprise-class solutions, are putting increased emphasis on capabilities such as SI and PI that smaller/cheaper competitors can’t match, and also focusing on system design challenges that are encountered by every product engineering team who is creating complex, modern electronic systems.
It will be interesting to watch the evolution of design and analysis tools as yesterday’s “board” tools become tomorrow’s “system” tools. Companies like Cadence and Mentor/Siemens who are in the board/system business as well as the IC design business have significant amounts of technology that can span domains, and that should play to their advantage as these tools and flows become more integrated, complex, and sophisticated. System level design encompasses functional, mechanical, thermal, SI, PI, power, and several other domains, all of which will eventually need to be analyzed and optimized in concert. The company that comes up with the best way to orchestrate that symphony should have a nice ride.