It’s no secret that ASIC and ASSP designs are getting more complex. First, there’s that whole thing about Moore’s Law allowing design teams to put more transistors, gates, memory cells, transceivers, processors, and acceleration engines on a chip. And, if that weren’t enough, there’s the relatively new quest to stuff an increasing number of chiplets into a package, tying them all together with 2.5D or 3D packaging techniques. The result is a geometric or exponential complexity increase for logic, power distribution, and thermal dissipation.
Less well known, perhaps, is that the current level of first-time success with ASIC designs is a dismal 24 percent, down from 31 percent in 2014, according to a 2022 Functional Verification Study done by Wilson Research Group and Siemens EDA. That’s the lowest level recorded in the past 20 years. As a result, according to this same study, only 36 percent of ASIC projects finish on schedule. The consequences include additional development costs as the projects run past deadlines and, possibly worse, miss market windows. Some missed market windows are worse than others – the Winter holiday selling season, for example.
What about FPGA-based designs, you ask. After all, the hard part of an FPGA-based design, the silicon, is finished before the system design starts (at least in theory). Sadly, this Functional Verification Study says that FPGA-based design is actually in worse shape than ASIC design, with only 30 percent of projects meeting their deadlines. I have a theory about this, not suggested by the study: FPGA design teams tend to be less scrupulous about simulation and verification because the expense of fixing a bug in an FPGA-based design is not nearly as high as for ASIC and ASSP designs. However, that’s just an educated guess. I don’t have a survey to back that up, but I have plenty of anecdotal data to support my theory.
Siemens EDA believes it has a solution to these challenges. The company has announced a product extension to its verification tools. The latest and greatest tool is called Questa Verification IQ with today’s most desirable software ingredients: AI/ML (artificial intelligence and machine learning). According to Siemens EDA, ASIC and ASSP design teams now spend seven to eight months in design verification, and that period continues to stretch as new aspects of a design now need verification. Safety verification, for example.
The secret to this solution is data – lots and lots of data. A complex ASIC design project or even a design project based on an FPGA generates plenty of data. Every design iteration undergoes its own set of tests, and every test generates reams of data. Data is a result for many simulation activities including logic simulation, device emulation tests, analog and mixed signal simulation, static and formal verification, and functional-safety verification. There’s plenty of information in that data, and that’s information that the design team can use to zero in on a final design. The trick is teasing the relevant information out of that mound of data.
Collaborative tools within the Questa Verification IQ solution include:
- Testplan Author: a test plan editor
- Regression Navigator: a front end for the Siemens EDA regression engine
- Coverage Analyzer: applies AI analytics to test results to gauge and visually display coverage closure through heat maps, distribution and network graphs, and expression trees
- Verification Insight: a dashboard builder, used to display verification metrics, trends, and historical data across multiple project histories
Questa Verification IQ collects and unifies data from the formal and simulation engines within Siemens’ Questa platform, its OneSpin formal verification software, the Symphony platform for analog and mixed-signal simulation, and Siemens’ Veloce hardware for emulation and prototyping. The AI/ML capability in Questa Verification IQ analyzes the collected data to predict patterns and holes, identify root causes, and prescribe solutions to potential problems using the unique pattern-matching and prediction capabilities of AI/ML. The end goal is to improve the development team’s design efficiency by giving it all the information required for design signoff.
It’s apparent, even to a casual observer, that all this testing and verification immediately creates a big-data situation. Collecting, sorting, organizing, and then analyzing all this data for the purpose of driving to design closure presents a huge challenge. That’s why the Questa Verification IQ tool is plugged into Siemens’ Polarion REQUIREMENTS software, a platform that automatically captures all data from every engine run across the life of a development project. That data is then used to manage development of requirements, coding, testing, and finally product release across the entire design and verification process.
Siemens purchased long-time EDA provider Mentor Graphics back in 2017. At the time, Siemens issued a press release that said, in part, “Mentor is now part of Siemens’ product lifecycle management (PLM) software business, making the combined organization the world’s leading supplier of industrial software used for product design, simulation, verification, testing and manufacturing.” Although the company was perhaps telegraphing the message, that general wording did not click with me at the time. I credited Wally Rhines’ salesmanship for Mentor’s sale to Siemens. Perhaps overly so, but if you know Rhines, you can understand why I might have thought this way.
However, with the introduction of Questa Verification IQ, it’s clear that Siemens has transformed the design process for ASICs, ASSPs, and FPGA-based systems into a big-data problem and has harnessed its big-data tool, Polarion, to tie several former Mentor EDA tools together. Siemens has also applied AI/ML pattern-matching to help develop test plans and regression tests, analyze test coverage, develop insights, and draw some useful conclusions about this giant pool of data.
Questa Verification IQ is a browser-based EDA tool, which means that it needs only to be installed on a server somewhere. Currently, that means either an on-premise enterprise server or a cloud-based server under the control of the enterprise. Although Siemens does not currently offer Questa Verification IQ as a service, the company may choose to do so in the future, according to Darron May, the software’s Product Manager at Siemens. In addition, Questa Verification IQ is not strictly limited to Siemens development tools, according to May. Because it’s standards-based, the tool can interface with tools from other EDA vendors.
This integration capability takes me back to 1991, when Mentor Graphics announced its Falcon Framework, a way of integrating EDA tools together. That attempt, more than 30 years ago, was perhaps a bit ahead of its time. EDA frameworks never really took off back then. However, today, we have a different story.