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RISC-V: The Groundswell Continues

The Faithful Gather in Santa Clara

“Faith is taking the first step even when you don’t see the whole staircase.” – Martin Luther King, Jr.

It’s interesting to attend a religious revival meeting when you’re not a member of that particular denomination. It’s a bit like attending a political rally as an outsider, or buying tickets to a live concert even though you hate the band but your date really wants to go. You smile and make polite conversation with the attendees, all of whom have something in common. And, in the end, you might come away with a new appreciation of their beliefs, their politics, or their taste in awful music.

So it was at last week’s RISC-V Summit, a four-day love-fest in the city named for Saint Clare in her eponymous California Valley of Heart’s Delight. What all the exhibitors and speakers had in common was a deep financial commitment to the new-ish RISC-V processor architecture. Apart from that, however, their opinions, their motivations, and their convictions were all over the map.

RISC-V, of course, is “that Berkeley academic project,” a free and open-source (mostly) 32-bit RISC processor. As a CPU architecture, it sorta competes with ARM and MIPS and other licensable processor designs. And several people I spoke with were quick to compare RISC-V to those other processors, extolling the virtues of their chosen architecture and the shortcomings of all the others.

So why did all these assembled vendors choose RISC-V? Three reasons, mostly:

It’s Free

There’s no getting around the fact that RISC-V is free. There are no licensing fees and no royalties. It’s free as in “free beer.” It’s the Linux of CPU designs. In fact, you don’t even have to click through any agreements or join any mailing lists to start using RISC-V. You can secretly download all the specs and start designing your own RISC-V implementation in complete stealth mode, if you want to. (The only caveat is that you can’t use the “RISC-V” name unless you pass the compliance testing, which requires some paperwork.) It’s about as free and unencumbered as hardware specifications get.

But, like Linux, there’s free, and then there’s free of charge. A decade ago, zillions of software developers flocked to Linux because they saw it as a zero-cost alternative to commercial, paid, operating systems. But the amount of work required to port and test each of those Linux implementations made the “free” operating system very costly in terms of manpower and lost productivity. Commercial operating systems didn’t go away, and even Linux distributors charged for their services. IBM is paying $34 billion for Red Hat.

So, creating your own RISC-V implementation isn’t the work of a moment. The free download gets you an instruction set architecture (ISA) and some open-source tools, but not much else. Sure, it saves you the trouble of creating your own ISA from scratch, but that’s a far cry from a detailed microarchitecture, a circuit design, or a verification suite. You still have to design the CPU.

Alternatively, you could use freely available core designs like PULP, which a few of the exhibitors at the conference readily admit to using in their commercial products. Or spend real money and choose from among several commercial RISC-V core implementations from SiFive.

Nobody likes to admit that they chose a product because of the price, and that was evident from talking to the vendors at the show. “Price was second or third in priority” was a common response. But a few were more blunt, or more honest. They relished the idea of adopting a new CPU family and never again writing a check to ARM. “It saves me hundreds of thousands of dollars. And all the headaches,” said one.

It’s Extensible

RISC-V takes a pretty lackadaisical view about user-customization. That’s in stark contrast to ARM, MIPS, and most other commercial CPU families, which absolutely prohibit nonstandard extensions to the architecture. All ARM features, extensions, and instructions are created by ARM, thank you very much, and licensees get exactly what ARM has created. On the one hand, that guarantees (more or less) that all ARM implementations will be binary compatible with one another, which helps with software standardization and portability. On the other hand, it makes it hard to differentiate your Cortex-A53 device from your neighbor’s.

Nearly all the silicon vendors said that extensibility either was the main reason they chose RISC-V or was in the top two (the other being performance). They liked the idea of creating new in-house features here and there, adding their secret sauce where appropriate. Some have already done so – Esperanto Technologies is an extreme example – while others are keeping their customization ideas in their back pocket, to be deployed somewhere down the road. I suspect that many will never develop custom extensions; they just like the idea that they could.

So far, the RISC-V Foundation (the body that maintains the architecture) has done a good job of reining in incompatible extensions that would fragment the CPU’s nascent software base. It would be awfully easy to allow each RISC-V licensee to go their own way, creating mutually incompatible approaches to the same problem, dozens of different times. While that’s technically possible – again, there’s no official licensing required, so there’s nothing to stop a renegade design team – the Foundation members work to avoid that. Extensions, enhancements, and additions are discussed in committee, out in the open, and agreement is arrived at by consensus, not by fiat. Thus, any active RISC-V Foundation member (there are more than 130 organizations and dozens of individuals represented) will be aware of what’s going on and can vote to adopt or reject any changes. The majority rules, so you might not get what you want, but at least you’ll know it’s coming.

“Design by committee” sounds like a recipe for disaster, but it seems to work for this group. The architecture is modular, with a baseline spec implemented in all RISC-V cores that provides a software base for compilers, operating systems, and tool chains. Then there are optional add-on packages, such as for floating-point support, security, and other features. Some modules are designed, debated, and adopted in a relatively short amount of time, and their committee disbands. Others, like security features, are produced by standing committees whose work is never done. There are no formal leaders to these committees, nor for the group as a whole. It’s an entirely democratic process wherein each member gets one vote. “Democracy,” as Winston Churchill and others before him have said, “is the worst form of government, except for all the others.”

It’s Actually Pretty Good

Predictably, most RISC-V vendors at the RISC-V Summit said that RISC-V was “actually pretty good.” But the words were spoken with a tone of surprise, as if nobody there had really expected the processor to be useful, practical, or even functional.

That’s easy to understand, given RISC-V’s gestation as “yet another academic toy.” Indeed, its roots reach back to a synthetic teaching tool for Hennessy & Patterson’s landmark textbook. Like the Pascal programming language, it wasn’t intended to be a real thing. RISC-V is the fifth generation of this ISA, as the name suggests.

The other hint is also right there in the name: reduced instruction set. It’s very basic. Yet more than one hardware designer told me that his group was impressed with RISC-V’s benchmark results. For such a simple machine, it does the job. And it’s extensible. And it’s free. They were sold.

Even other CPU designers like it. A big company like nVidia has no shortage of talented CPU architects and designers, but they voluntarily chose to use RISC-V. Didn’t the CPU design team revolt at the idea of abandoning their own in-house CPU – their baby – to adopt some freebie giveaway design? “No, it was their idea,” said Frans Sijstermans, nVidia’s VP of Engineering. “They saw the benchmarks and they were convinced.”

Other silicon vendors told a similar story. RISC-V was capable enough to do the job. And, if not, they felt they could enhance or extend it if necessary. “CPU architecture is not where we innovate,” was a common refrain. “Our value lies elsewhere, so why spend time developing our own CPU or paying [royalties] for somebody else to do it? RISC-V works, it’s cheap, and it’s well supported. Done.”

If only all conversions were so rational.

2 thoughts on “RISC-V: The Groundswell Continues”

  1. Yes indeed, there is not a dimes worth of difference between ALL of the RISC ISAs.
    There is a load instruction for each operand, a store for the result, and a fetch of the instruction that does the operation.
    The actual performance is determined by the memory system. Caches supposedly reduce the acces to memory(at least according to common knowledge which is mainly hype).
    Then there is more hype about the wonderfulness of branch prediction and out of order execution.
    Which is all intuitive as shown by the popularity of accelerators and GPUS.

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