Back in February, we previewed the new Xilinx Zynq UltraScale+ RFSoC. At the time, we were pretty optimistic about the potential of these devices, as they promised to deliver some very high-value integration of the analog and digital components of a 5G RF signal chain. Well, apparently, the “preview” days are over, because, this week, Xilinx is releasing the details of the new family as well as announcing shipments to tier-1 customers “developing multiple 5G end-applications, cable access remote-PHY nodes, and Electronic-Warfare / Radar applications.” The company says that the new devices are also applicable to a wide range of additional applications, including test & measurement, SatCom, and military radio.
To review, the Zynq UltraScale+ RFSoC is a monolithic integration of RF sampling ADCs and DACs into the Zynq UltraScale+ SoC. This integration delivers significant reductions – Xilinx claims 50-75% – in system power and footprint for radio applications. Yep. That would be a big deal.
In conventional implementations, applications such as 5G radios would use a conventional SoC (or, in many cases, an unconventional SoC/FPGA hybrid such as Zynq) combined with discrete ADCs and DACs, plus analog filtering and down conversion to an intermediate frequency. The analog section would bring in signals from the antenna and prepare them for digital processing by the SoC. By integrating the ADCs and DACs directly on the SoC silicon, the need for down conversion is eliminated, and most of the filtering can be done in the digital domain in the SoC section.
On the footprint front, we end up with a single chip rather than an SoC plus numerous ADCs, DACs, and analog processing components. This reduces the footprint by approximately half. It also dramatically simplifies the board design, as RF signal paths don’t have to be routed through numerous components, and SerDes transceivers don’t have to be employed to get data from ADCs into the SoC, and from the SoC back to DACs. This elimination of SerDes channels, additional components, and numerous IO paths between components and PCBs also cuts power consumption, again by approximately half.
Moving the signal conditioning from the analog domain into the digital domain has payoffs as well. Analog components can be temperature sensitive, and compensation for variability can be tricky. Using DSP techniques instead, we can improve performance and reliability as well as simplifying the design process – another win for the integrated solution.
The RF section of the new RFSoCs includes eight 4 GSPS or sixteen 2 GSPS 12-bit ADCs, with digital down-conversion (DDC), and eight to sixteen 6.4 GSPS 14-bit DACs, with digital up-conversion (DUC). This allows direct RF sampling for flexible analog design, greater accuracy, and lower power.
The SoC section is pretty much a standard Zynq UltraScale+ SoC, but with a few optimizations for RF applications. The devices each include a quad-core 1.5 GHz ARM Cortex-A53 applications processor, a dual-core 533MHz ARM Cortex-R5 real-time processor, a DDR4 2600 MHz memory subsystem, platform, power, and system management functions, security, 930K LUT4-equilvalent (678K in the ZU25DR variant) of FPGA fabric, 4,272 DSP blocks (3,145 in the ZU25DR variant), sixteen 33G SerDes transceivers (8 in the ZU25DR variant), PCIe Gen3 x16, PCIe Gen4, and 100G Ethernet. Whew! That’s a lot of stuff on one chip. Missing is the GPU found on other Zynq devices, which didn’t have a clear role in RF applications.
In addition to the SoC and RF section contents above, Xilinx has added eight integrated SD-FEC blocks to two of the devices (the ZU21DR and the ZU28DR). The SD-FEC includes a low-density parity check encoder/decoder which meets 5G, DOCSIS 3.1 specifications, a shared memory subsystem, and “Turbo Decode” for 4G LTE-Advanced and 4G LTE-Pro compliance. Xilinx says that the SD-FEC delivers 10x-20x the performance of the same functions implemented in soft cores in FPGA fabric at 80% less dynamic power. The SD-FECs bring up to 42 Gb/s LDPC encode and 10 Gb/s decode system throughput, customizable LDPC codes for evolving standards and differentiation, and soft-decision decoding for greater reliability.
The RFSoC family is made up of five devices, each targeting a specific set of applications. The ZU21DR, aimed at baseband, dispenses with the ADCs and DACs, but includes 8 SD-FECs. The ZU25DR and ZU27DR are intended for wireless radio, and they bundle 8 each of the 12-bit 4GSPS ADCs and 14-bit 6.4GSPS DACs with either 678K or 930K LUTs, 8 or 16 33Gbps SerDes, and 3,145 or 4,272 DSP blocks. The ZU28DR device targets backhaul and remote PHY applications with the same resources as the ZU27DR, but with the addition of 8 SD-FECs. Finally, the ZU29DR addresses phased-array radar and radio applications with 16 of the slower 2GPSP ADCs (rather than 8 of the 4GSPS blocks) and 16 DACs.
Speaking of the FPGA fabric, Xilinx has also rounded up a rich portfolio of IP and reference designs for each of their target application areas. The capabilities of the SoC combined with the off-the-shelf IP blocks should significantly shorten initial bring-up cycles for design teams. Of course, there is also a robust set of development and evaluation boards, as well as tool support in the standard Xilinx design tool suite.
Xilinx appears to be running unopposed in this RFSoC space, and it’s unlikely that any ASSP or custom solutions will threaten them any time soon. The benefits of RFSoC are compelling enough that it appears that the company could easily establish a dominant position in the RF signal chain in many of these rapidly-expanding application areas, particularly because the Zynq devices have already established a beachhead there.
In the ongoing duel between Xilinx and Intel/Altera, Xilinx appears to be reaping the rewards of a strong emphasis on their SoC families. While Intel offers a very capable line of FPGA SoCs, we haven’t seen the kind of penetration into high-growth application areas that Xilinx appears to be achieving. At the same time, Intel is obviously working hard on other key applications of programmable logic, such as data centers.
We have long since passed the point where building a better FPGA was enough to capture market share. Today, each application area requires a comprehensive solution of parts, tools, IP, reference designs, development platforms, and focused marketing. Because we are currently in a highly unusual “knee” in the programmable logic market with numerous new high-value applications emerging, it will be interesting to watch how the two companies allocate their resources and place their bets, prioritizing investment in the far-too-many opportunities.