feature article
Subscribe Now

Radio FPGA!

Xilinx Announces RFSoCs

CQ CQ CQ – Calling CQ. This is 5G calling…

We’ve all heard it. 5G is coming. Maybe not soon, but as soon as we can get all those pesky technical issues worked out. Which pesky technical issues would those be? Glad you asked. It turns out that cramming a previously unfathomable amount of bandwidth over an unprecedented number of individual connections into each and every cell tower using millimeter wavelengths and 2 dimensional massive multiple-input multiple-output (MIMO) antenna arrays – and doing all of that within acceptable power and footprint constraints – is a really tough problem. Actually, it’s a LOT of really tough problems.

As bandwidth demands have increased, we have moved the radios ever closer to the antennas. With 5G, the number of antennas is exploding – into large 2D antenna arrays – and the radios will need to be pretty much inside them. And, instead of burning a few paragraphs here on esoterica such as beamforming and the remarkable amounts of signal processing that will be required to connect exponentially more people and more things wirelessly to the internet, using RF spectrum more efficiently than we do today, let’s agree to just take it as a given that we want to do a lot of heavy-duty digital work very, very close to the RF section of our 5G systems.

How close?

Xilinx says – all in the same, monolithic chip. That’s how close.

This week, Xilinx is announcing what the company is calling the “World’s First All-Programmable RFSoC.” The new devices will be based on the same architecture as the impressive new Zynq UltraScale+ MPSoC FPGAs, but will include integrated RF-class analog technology on the same piece of silicon. Zynq’s combination of multiple, heterogeneous, conventional processors, including multi-core 64-bit applications processors, real-time processors, graphics processing units, embedded memory, FPGA fabric, DSP blocks, and high-speed IO have already made it a very likely critical component of the 5G infrastructure.

Zynq devices would obviously be cast in roles where digital acceleration of DSP functions could be closely integrated with Zynq’s embedded processing capabilities. The FPGA fabric, with its embedded hardened DSP blocks, can perform massively parallel DSP functions much faster, and (more importantly) with much less power, than conventional processors, leaving the follow-up work and overall control to embedded software running on the built-in ARM processors. But the RF section of that signal chain is still less than optimal. RF would need to go through analog conditioning, then ADCs, and then through two sets of SerDes transceivers in order to find its way into the digital realm of the Zynq device.

With the new RFSoCs, Xilinx is building the analog into the Zynq device, in the form of high-performance, high-resolution ADCs and DACs feeding directly into the Zynq interconnect fabric. For each channel, this saves a discrete ADC and DAC, plus two sets of high-speed SerDes transceivers (one on the Zynq device and one attached to the ADC/DAC). Now, the RF can be brought directly into the RFSoC, with a significant reduction in total power consumption and board footprint. The new Xilinx chips will be capable of direct RF sampling with “many channels” of 12-bit ADCs operating at up to 4GSPS with digital down-conversion and 14-bit DACs operating at up to 6.4GSPS with digital up-conversion. 

Xilinx claims that the power savings on a radio digital front-end will be in the realm of ~50% compared with a discrete implementation: 41% for a 4×4 implementation running at 100MHz, and 51% for an 8×8 implementation. Regarding footprint minimization, Xilinx claims about a 52% reduction with a 4×4 radio, and a 77% reduction on an 8×8 radio. This is assuming that the RFSoC is in a 35mm x 35mm package and the RF DACs and ADCs required for the discrete implementation are about 15mm x 15mm each. In addition to the power and footprint advantages, there are obvious potential advantages in reduced board complexity, lower manufacturing cost, and system reliability. 

Not quite as obvious is the opportunity to make more of the signal processing happen in the digital domain rather than in analog. By moving the RF portion into the SoC, we can eliminate some reliance on expensive, high-precision, temperature-sensitive RF analog components for pre-conditioning the signals before the ADC stage. Again, this reduces system cost and complexity, and it simplifies the overall design process.

Because Xilinx is putting the analog and digital parts of the RFSoC on the same slab of silicon, they had to blaze some new trails in engineering the analog portions in 16nm FinFET CMOS technology – not exactly the process of choice for mainstream RF/analog design. The upside, of course, is that some of the performance and power efficiency benefits of the FinFET process also help out on the analog side. If Xilinx did their homework right, the resulting device should be a major win in 5G system performance and simplicity. 

Of course, 5G radios are not the only potential use for RFSoCs. There is a wide spectrum of applications that can benefit from integrated RF-quality analog on an MPSoC with FPGA fabric and programmability. But, market-wise, 5G deployment is obviously a huge opportunity for Xilinx. Xilinx says they have test chips of the new RFSoC devices, the product is in the pre-release stage, and more details and specifications will be available later this year when the formal announcement is made. Meanwhile, the company is already working with key 5G development partners. Interestingly, there is no apparent competition for these new Xilinx devices in this early stage of 5G development. And, because of the importance of programmability – both hardware and software – in this application, the sockets Xilinx wins could be very hard to replace with a future ASIC or ASSP.

Platforms such as Zynq are remarkably powerful bases on which to build what amounts to flexible, programmable ASSPs. In this case, it appears that Xilinx has been able to make a modest addition to a proven product in order to create a new device with game-changing capabilities for its target application. It will be interesting to see what additional variants come out as new market and technology opportunities present themselves.



3 thoughts on “Radio FPGA!”

Leave a Reply

featured blogs
May 27, 2020
Could life evolve on ice worlds, ocean worlds, ocean worlds covered in ice, halo worlds that are tidally locked with their sun, and rogue worlds without a sun? If so, what sort of life might it be?...
May 26, 2020
I get pleasure from good quality things. Quality is a vague term, but, to me, it is some combination of good design for usability, functionality and aesthetics, along with reliability and durability. Some of these factors can be assessed very quickly; others take time. For ex...
May 26, 2020
#robotcombat #combatrobots #robotwars #WeWantSeason5 #WeGotSeason5 These are some of the most popular hashtags used by a growing number of global BattleBots enthusiasts. Teams from all backgrounds design, build and test robots of all sizes for one purpose in mind: Robot Comba...
May 22, 2020
[From the last episode: We looked at the complexities of cache in a multicore processor.] OK, time for a breather and for some review. We'€™ve taken quite the tour of computing, both in an IoT device (or even a laptop) and in the cloud. Here are some basic things we looked ...

Featured Video

DesignWare 112G Ethernet PHY IP JTOL & ITOL Performance

Sponsored by Synopsys

This video shows the Synopsys 112G Ethernet PHY IP in TSMC’s N7 process passing the jitter and interference tolerance test at the IEEE-specified bit error rate (BER). The IP with leading power, performance, and area is available in a range of FinFET processes for high-performance computing SoCs.

Click here for more information

Featured Paper

Energy-Saving Piezo Haptic Driver is the Touch Sensor's Best Friend

Sponsored by Maxim Integrated

Haptic sensing technology, with its ability to render complex tactile experiences, is becoming popular in portable applications. Excessive power dissipation is a concern with current piezo haptic drivers' implementations. Although the piezoelectric actuator represents a capacitive load, considerable power is dissipated to drive it. This design solution reviews the shortcomings of current piezo haptic driver implementations and introduces a novel, regenerative, boost converter-based implementation that minimizes power dissipation, helping maximize the battery life of portables.

Click here to download the whitepaper