feature article
Subscribe Now

Punching Above Their Weight, Achronix Beats the Odds

We first met Achronix back in 2004 and have been following them constantly for sixteen years now. We’ve seen the company go from a founder-funded startup developing revolutionary asynchronous FPGAs in New York using technology licensed from Cornell – to an innovative, successful, mature, Silicon Valley fabless semiconductor and IP company giving the likes of Intel and Xilinx constant trouble in the programmable logic market and staking out a bold swath of eFPGA IP, chiplet, and accelerator board territory. 

Throughout their history, Achronix has perfected the pivot, executing a sequence of smart marketing moves in usually-successful attempts to outflank their much larger competitors. During the two decades Achronix has been around, numerous other programmable logic startups have failed, careening headlong into the wrath of the Xilinx-Altera/Intel duopolistic juggernaut. Achronix has consistently beaten those odds and survived and thrived with well-timed, unexpected pivots in their strategy. 

Early on, Achronix back-burnered their asynchronous FPGA technology (which, as an aside, looked suspiciously similar to the HyperFlex architecture later introduced by Altera, and now used in Intel’s FPGA fabric.) Instead, Achronix went with a more conventional FPGA architecture and focused on optimizing their choice of hard IP much more carefully than Xilinx and Altera. At the time, the two large players were pursuing a “kitchen sink” strategy, trying to outdo each other by equipping their devices with every type of hardened IP block that any customer in any application might need. Instead, Achronix focused on a narrower set of applications and were able to optimize their devices in a way that gave them some compelling differentiators for certain high-value applications. As a result, the company won a number of sockets that would have normally gone to the big guys uncontested.

As a much smaller company, Achronix was still fighting an uphill battle on several fronts – one of which was process technology. In 2010, they surprised the industry by moving to Intel’s contract fab for their Speedster 22i family, a move that allowed them to take advantage of the significant process technology advantage that Intel enjoyed at the time. It made them the first vendor to offer FinFET technology in an FPGA – a major coup against the larger competitors who historically pride themselves in gaining any measure of process technology advantage. It also gave them several years of strategic wins, and enough time to get them to their next major pivot.

In 2016, Achronix dropped another bomb – pivoting in a way that their competitors most likely will never match. They took the extraordinary step of offering their FPGA technology as IP. While there were already several eFPGA companies competing in the IP market, Achronix was the first bona-fide competitive FPGA company to cross over the line into licensing their FPGA fabric for use in custom chips. 

FPGAs have historically maintained very high margins in the chip business, and one of the ways FPGA companies have always defended those margins is by owning the chip. If you wanted leading-edge FPGA fabric, you had to buy an FPGA. There was no reasonable path to make your own to include in your ASIC or ASSP. That meant, if you wanted an SoC with FPGA fabric and other important blocks – processor cores, memory resources, fancy IO, or whatever – you had to buy an FPGA that included those things, pay the high margins the FPGA companies demanded on their silicon real-estate, and settle for whatever engineering compromises the FPGA company made in putting those blocks on the chip. You probably also had to buy a larger, more expensive FPGA than you would have otherwise needed, just to get the right mix of IO and IP blocks your design required. And, you probably ended up with a chip that had a lot of extra stuff on it you didn’t need, for the same reasons.

By offering FPGA fabric as IP, and the ecosystem required to make use of it as services, Achronix broke that chokehold. Companies with the wherewithal to design their own ASICs could now design the chip they really wanted, rather than choosing an expensive, sub-optimal one from the off-the-shelf offerings of the FPGA companies. And, because Achronix was already offering that fabric and ecosystem in stand-alone form in their FPGAs, customers could take advantage of a smooth integration path, starting with the stand-alone FPGA in their system, and then migrating to an integrated, improved, cost-reduced system where the FPGA fabric was merged into their own SoC. 

At about the same time, Achronix announced plans to release FPGAs in chiplet form, which would allow package-scale integration of FPGAs with other chiplets in a system-in-package (SIP) configuration. This was also a prescient move, as the industry is rapidly forming an ecosystem that will allow custom devices to be assembled from chiplets of various types, mixing and matching different process technologies and even chiplet vendors. Again, this provides options other than stand-alone FPGAs for systems companies wanting more integration and performance.

In 2019, Achronix rolled out their current flagship FPGAs – Speedster 7t – a high-performance line aimed at AI and other demanding acceleration workloads. Fabricated on TSMC’s 7nm process, the devices feature a new 2D network-on-chip (NoC) with specs arguably better than those of the NoC on Xilinx’s Versal devices, an array of new machine learning processors (MLPs) optimized for artificial intelligence and machine learning (AI/ML) workloads, GDDR6 interfaces (an interesting counterpoint to the HBM solutions offered by their competitors), and 400G Ethernet and PCI Express Gen5 ports. In every way, Speedster 7t is a solid competitor to the current flagship offerings from Xilinx and Intel. 

Achronix is also partnering with BittWare in the ready-to-use board market, with their VectorPath S7t-VG6 data-center-class accelerator cards aimed at specific types of networking/acceleration workloads. The S7t-VG6 includes a Speedster 7t FPGA. Built with a double-density QSFP-DD cage, the board supports “up to 1x 400GbE or 4x 100GbE using the 56G PAM4-enabled Speedster7t device. An additional QSFP port supports 2x 100GbE, and a 4x OCuLink connector supports NVMe attached storage. Sixteen channels of GDDR6 graphics DRAM handle high-bandwidth memory requirements, providing up to 512GB/s.” The net result is that end customers can drop VectorPath into their system and immediately get the benefits of the FPGA’s power without going through the process of designing the high-speed interfaces required to feed the beast.

With their multi-pronged strategy of high-end FPGA devices, eFPGA IP, chiplet packaging, and ready-to-run accelerator boards, Achronix have positioned themselves well as a spoiler against their larger, but arguably less nimble, competitors. It will be interesting to watch how the eFPGA strategy plays out in particular, as it gives the company a strong edge that will engage customers in a mode that the competition most likely cannot (or will not) choose to match. 

Leave a Reply

featured blogs
Jan 19, 2021
If you know someone who has a birthday or anniversary or some other occasion coming up, you may consider presenting their present in a Prank-O gift box....
Jan 19, 2021
As promised, we'€™re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro ® Package Designer... [[ Click on the title to access the full blog on the Cadence Communit...
Jan 19, 2021
I'€™ve been reading year-end and upcoming year lists about the future trends affecting technology and electronics. Topics run the gamut from expanding technologies like 5G, AI, electric vehicles, and various realities (XR, VR, MR), to external pressures like increased gover...
Jan 14, 2021
Learn how electronic design automation (EDA) tools & silicon-proven IP enable today's most influential smart tech, including ADAS, 5G, IoT, and Cloud services. The post 5 Key Innovations that Are Making Everything Smarter appeared first on From Silicon To Software....

featured paper

Overcoming Signal Integrity Challenges of 112G Connections on PCB

Sponsored by Cadence Design Systems

One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).

Click here to download the whitepaper

Featured Chalk Talk

Cloud Computing for Electronic Design (Are We There Yet?)

Sponsored by Cadence Design Systems

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

More information about the Cadence Cloud Portfolio