Introduction

Managing the increasing complexity of today’s digital applications calls for new design strategies. Risk, cost and time-to-market (TTM) can make or break a product development. While many designers are turning to FPGAs to reduce risk and improve TTM, the staggering per unit cost of high-density FPGAs quickly becomes intolerable for even low volume applications. Cell-based ASIC solutions offer much lower per unit cost, but the NREs for deep sub-micron technologies are becoming cost prohibitive. Structured ASICs fill the gap by offering excellent per unit cost and reasonable NREs. This paper describes … Read More → "High-Density FPGA-to-ASIC Conversions using Structured ASIC: Fills the Gap"

There’s something of a Renaissance going on at Lattice semiconductor right now. Since forming their partnership with Fujitsu about a year ago, the company has sustained a steady stream of relevant announcements of new, competitive product lines. Not content to stay put in the commodity CPLD business, Lattice is mounting an aggressive campaign to capture a share of the emerging value-based FPGA market.

This week, Lattice stepped up their attack with the announcement of their new Lattice-XP line. Continuing the recent “Wolf in Sheep’s Clothing” trend in flash-based programmable logic, this … Read More → "Lattice Launches XP"

It probably started innocently enough. A few years ago, an application note from a Xilinx engineer described the implementation of a small processor that could be used as a microcontroller in designs with complex FSMs. That little piece of soft-IP (now known as PicoBlaze) was quite handy, and it found rapid and widespread acceptance among designers. As with any good idea, though, engineers just couldn’t leave it alone. Soon there were requests for wider, faster, more robust processor cores running on FPGAs, and marketers were more than happy to oblige. While it may have been easy … Read More → "Prime-time Processing"

The emergence of affordable high-end FPGAs is making them the technology of choice for an increasing number of electronics products that previously were the exclusive domain of ASICs. Offering unprecedented levels of integration on a single chip, today’s programmable devices have widely expanded the size, scope, and range of applications that can now be deployed on them .

To ensure a fast and efficient implementation of these advanced, feature rich FPGAs, designers need access to the latest in productivity enhancing electronic design automation (EDA) tools and methodologies. For years, hardware/software (HW/SW) co-verification has been … Read More → "Co-Verification Methodology for Platform FPGAs"

There is a radical shift in the beliefs about high speed serial feasibility as it moves beyond 3 Gbps on up to 10 Gbps. In a matter of few short years, the industry has gone from saying “impossible” to the concept of 10 Gbps with existing CMOS NRZ signaling to today, where all the required productized elements are in place for delivering manufacturable systems operational anywhere from 2.5 to 10Gbps. These components include: off the shelf transceivers, backplanes and connectors.  The reason for this shift has been a concerted, partnered effort by all parties including semiconductor vendors, backplane, connector manufacturers and signal … Read More → "Making the Jump to 10G"

A little over a year ago, when we wrote our last feature on high-speed serial I/O, you might have felt safe. You could read the article with a secure fascination, isolated from personal involvement with the risks of the technology and amused at the lengths to which those telecom types would go in order to cram more bandwidth onto the backplane – safe in the knowledge that your own precisely-tuned parallel busses were merrily megabitting away on your little low-tech circuit boards. Now, the subject may feel a bit more uncomfortable. With standards like PCI Express gaining increasing momentum, … Read More → "Breakthrough Bandwidth"

FPGA designers are typically working with prototype designs without much synthesis history, so on the first pass of the design they will not have developed a set of false path and multi-cycle path constraints. FishTail’s Focus tool can generate false path and multi-cycle path timing exceptions for the FPGA designer before the first synthesis run. These timing exceptions have the ability to improve FPGA QoR by relaxing constraints on the timing paths of the design and potentially allow the FPGA to run faster. In this paper we have studied the impact of timing exceptions on nine designs … Read More → "The Impact of Timing Exceptions on FPGA Performance"

Most of us picked up HDL design the way we discover a new city. We land at the airport, and a taxicab drops us off at some arbitrary location – a hotel perhaps. From that point, we branch out in an ad-hoc manner, discovering things mostly by accident, and gradually building a mental picture of the place for ourselves. Different people may develop entirely differing views of a place depending on when and how they landed there and how their luck went in this semi-random discovery process. Much of what you discover first is based on what you were trying … Read More → "Simulator Savvy"

Configuring and implementing an FPGA-based embedded system is not an easy task. Connecting various blocks of discrete intellectual property (IP) in a system using an FPGA, and making them all work together, continues to be difficult and time-consuming. Instead of designing a system themselves, engineers need a solution that can be quickly configured to closely match their design’s required functionality, for the lowest possible cost. A solution that combines FPGAs with a hardware-based system-on-module (SOM) approach makes this possible.

One of the major benefits of using an FPGA-based embedded system is the ability to re-use a … Read More → "FPGA-based System-on-Module Approach Cuts Time to Market, Avoids Obsolescence"

Nick Martin is not bound by high-tech tradition. If he were traditional, he’d have a PhD from Berkeley, UC Irvine, or MIT. If he were traditional, his COO would be an MBA from Stanford and Altium would be another venture-funded EDA company in a high-tech corridor like Silicon Valley, Research Triangle, or Boulder. If he were traditional, Altium’s tools would be 80% functional, they’d have no sales or distribution channel, and they’d be looking to be acquired by one of the three major EDA companies.

Instead, Nick is founder and … Read More → "Nick Martin"