On the fading footsteps of the fury of the Supercomputing conference, our minds typically whirl on the world of accelerated computation.  We picture powerful systems based on elegant devices that crunch through complex calculations at an almost inconceivable speed.  When we visualize that, of course, we don’t always think about the fact that the “sea level” of compute power is in an ever-increasing tide surge.  As the common desktop computer climbs ever higher in compute performance, many problems and applications that were once the purview of supercomputers have been conquered by the … Read More → "The New DSP"

“…It works the same as assertions in System Verilog,” he said. 

I quickly nodded my head — maybe too quickly.  “Oh, OK, I see,” I replied, almost before he had finished his sentence.

I wanted to give him confidence that the message was received so he would move on in the conversation.  If I looked puzzled, perplexed or confused – if I showed weakness or hesitation, he might linger in the lounge of this idea.  He might hang around here in the vicinity of trouble.  He might catch the scent of … Read More → "The Secret"

The High Performance Computing (HPC) community recognized the inherent limits of serial processing long ago. In the drive to continually improve the performance of HPC codes, programmers have explored a variety of alternatives, including employing new types of processors, coupling multiple processors, and parallel processing. Initially, these strategies were hindered by slow inter-processor communications and limited ability to parallelize algorithms. As a result, early attempts at alternatives to serial computation could employ only tens of processors. Over time, several innovations (including higher-bandwidth inter-processor links, algorithmic improvements that reduced the amount of data sent across those links, coarse-grain parallelism, and … Read More → "Computational Bottlenecks and Hardware Decisions for FPGAs"

Old wisdom says that too many cooks spoil the broth.  New wisdom says that accomplishing anything really big in high-tech requires a great deal of collaboration.  This week, new wisdom trumped old at the SDR forum as an unlikely coalition consisting of Texas Instruments, Xilinx, Green Hills, Objective  Interface, CRC, and even The MathWorks all had roles in producing a new platform for development of software defined radio (SDR) applications.

Software defined radio is developing into a benchmark challenge for the creators of technology.  The idea is simple enough – take the information … Read More → "Team SDR"

Design for portability is a valuable technique for engineers targeting consumer markets, seeking a cost-effective transition from an FPGA platform used for rapid development and prototyping to create price-competitive products that will win sales in fast paced consumer market.

Design Conversion for Marketing Objectives

FPGAs (field programmable gate arrays) provide a powerful tool for designers seeking to satisfy consumer demands for complex, multi-functional products. The FPGA’s fast development cycles accelerate the learning and debugging processes, which serves demands for short time-to-market that is characteristic of the consumer space. Initial … Read More → "Low-Cost ASIC Conversion Targets Consumer Success"

With the usual next-node battle cry of “power, performance, price, and productivity,” Altera sailed into sixty-five-nanometer territory today with the announcement of their much-anticipated Stratix III 65nm high-performance FPGA family. 

Altera has put considerable focus on power with this family, bringing in power-targeted architectural changes paired with powerful design tool support.  For years, power in FPGAs was not an important consideration.  The people paying the big bucks for older-generation FPGAs had power to burn along with their cash.  As times and technologies have changed, however, so has the power picture.  Millions of … Read More → "Stratix III"