He pauses for exactly the right amount of time, then whips into his delivery with energy and zeal – “Have youuuuu been struggling to meet ever-tightening design schedules with more complex designs and a smaller, leaner design team?” He picks up the pace, enunciating each word with perfect clarity. “Do youuuuu find that the RTL methodology is too cummmmmbersome for today’s more sophisticated FPGA designs?” He widens his eyes as he meets the gazes of each member of the audience, conveying an ominous fear. “Are youuuuuuu suffering the pain and ravages of MOORE’s LAW?!?”

The … Read More → "System-Level Sideshow"

Every time FPGAs hit a new process generation, there is a buzz. People want to hear about the underlying architecture, learn how fast the new devices will go, guess at how much logic they’ll hold, speculate on whether we’ll need a small nuclear power plant to operate them, and marvel at marketing’s ability to take something already quite impressive and exaggerate it to the point where we have no idea what it can actually do. We tingle with excitement. We wait a year until actual devices are available. Then, when the magic moment comes and we … Read More → "Tooling up for 65nm"

Engineers are trained problem solvers. While various fields of engineering require different types of technical training and expertise, the techniques of problem solving are universal to all branches of the profession. If engineers are problem solvers, could one infer that reverse engineers are problem creators? In a narrow view, probably so – but reverse engineering has its place in the innovation cycle as well. Reverse engineers also help us hone our security skills to prevent attacks from those who wish to do us (and our design IP) harm.

Reverse engineering is not a back-alley, cloak and dagger, … Read More → "Logic Lockdown"

The year is 2010. Alone in the kitchen, 8 year-old Mikey pulls a cereal container down from the cupboard. He presses the “open” button. A tiny camera with a wide-angle lens grabs an image. Inside the lid, a low-cost embedded system with hardware video processing locates Mikey’s key facial features in the image and creates an identification map. It then downloads from the household wireless network a current database of the family members allowed access to that cereal at this time of day. Mikey is on the “disallowed” list. The lock holds fast. A text notification is already on its … Read More → "Security Blanket"

Over the past few years, as FPGA devices have increased in density, speed, and started embedding dedicated memory, multiplier blocks, high performance intellectual property (IP), PLLs, and high-speed SERDES, they have become a viable alternative to implement complex designs and applications that traditionally targeted ASIC or ASSP-based designs . This trend however is stressing the limits of traditional FPGA static timing analysis tools and designer productivity is affected.

To meet market requirements and achieve target performance, FPGA design engineers are adopting new design styles and complex clocking schemes (i.e. clock multiplexing in 10M, 100M, 1G … Read More → "Complex ASIC Timing Verification Converges with FPGA-Based Designs"