Software defined radio is developing into a benchmark challenge for the creators of technology. The idea is simple enough – take the information coming in from an antenna and digitize it as early as possible. Then, the entire behavior of the radio can be handled and modified in the digital domain with the flexibility of software. Then (as the theory goes), hardware could be made very generic, and new radio standards could be quickly deployed and changed in the field without replacing hardware. One radio could do the work of many with greatly reduced cost, improved operational flexibility and much greater security.
That’s all in theory, of course. The reality is that huge technical barriers remain in the path of most design teams’ efforts to execute on that lofty vision. Each piece of the SDR puzzle is a formidable problem, pushing the limits of technology and engineering resourcefulness. The SDR challenge also spans a great number of disciplines, making a single-company, single-team solution almost infeasible.
This week, at the SDR forum, the aforementioned “A-list” array of companies announced a new, portable SDR development platform consisting of hardware, software, OS, tools, IP, and reference designs. System design teams developing SDR are the final partner in this massive collaboration and are the primary beneficiaries of the technology partnerships between these companies.
To appreciate the scope and depth of this teamwork, we really need to look at two axes of interest: the SDR platform itself and the design flow. This new SDR development kid includes important elements along each. Let’s start at the antenna and work our way down looking at the system, then start with concept and work our way to implementation looking at the design process.
The Small Form Factor Software Defined Radio Development Platform (boy, if we ever needed an acronym, but SFFSDRDP? Somebody needs to work on that part of the technology development.) is broadly targeted at the military, public safety, and commercial markets. It is sold and supported by Lyrtech, a Canadian company that specializes in DSP, and particularly in high-performance systems with DSP/FPGA combinations.
The platform comes in two basic configurations at two (or three, depending how you count) different price points. The base development platform – the SFF SDR DP weighs in at $9900, and the “reduced feature” evaluation version – DBB SDR EVM at $2900. There is also an “enhanced” version available that includes an SCA framework and ORB middleware. At either price point, the system is a steal if you’re working on applications that fit within its envelope. It would take only a tiny fraction of an average development team’s “roll your own” effort to justify the cost with everything this platform brings to the table. Throw in significant time-to-market advantages, and it’s almost a no-brainer.
The end customer profile that the SFF kit is targeting wants low power for battery operation, low cost for mass deployment, and small size and weight for maximum portability. The development kit itself is a very small form factor. Each stage is a separate board, and the three boards are piggybacked into a nice, manageable stack.
Functionally, TI takes the lead in the RF Module with support for half-duplex operation in both the 380MHz and 960MHz ranges and with 5MHz or 20MHz bandwidth.
The IF module contains TI ADC and DAC combined with a Xilinx Virtex-4 LX25 FPGA to pre-process data coming in from the ADC. The ADC consists of two ADS5500s with 14-bits at 125 Msps, and one DAC5687 16-bit dual-channel DAC with 500 Msps. Next, it’s off to the baseband stage where the action really heats up.
Unfortunately, however, the action normally heats up because the baseband stage is a major power hog. The processing power required to pull off the digital signal processing for SDR is formidable, and as anybody who went to this week’s Supercomputing conference can tell you – extreme processing power translates directly into power supply power. It is in this area that the new SFF SDR kit truly shines. As Amy Malagamba mentioned in our “SDR Pret-a-Porter” article earlier this year, one solution to the power glut in the SDR baseband stage is to take advantage of the extreme parallelism available in FPGAs.
However, where there is legacy software involved or for parts of the algorithm that don’t parallelize cleanly, DSP processors still provide many advantages. This kit forms an alliance between the two, taking advantage of the best capabilities of both devices. The baseband stage includes a Xilinx Virtex-4 SX35 FPGA connected to a TI DM6446 DSP-plus-ARM baseband and applications processor. Where heavy lifting is required, the FPGA can provide amazing levels of performance and power efficiency by parallelizing those functions, typically initial waveform processing, down conversion, and forward error correction. The SX family FPGA that is included in this stage is optimized for signal processing applications with a plethora of hardware multipliers embedded in special-purpose DSP math blocks. The TI DM6446 can then handle functions like demodulation, synchronization, filtering, and application-level control.
The DM6446 contains both a high-performance TI TMS320CC64x DSP processor and an ARM9 general purpose processor (GPP) as well as a full set of peripherals including serial ports, USB and Ethernet connections, and DDR2 and NAND-flash.
Power Design Flow
The trick to optimizing power consumption is finding a balance between what functionality is put into the DSP and what is accelerated into the FPGA. In most development methodologies, this is a one-time guess-and-go process, or an estimate based on estimation tools with dubious accuracy. In this kit, however, the board is instrumented with hardware power measurement that can return the actual power consumed in both the FPGA and the DSP. Design teams can then iteratively repartition their functionality between the two processing elements to reach the best compromise of power, performance, and ease of programming.
While this hardware-in-the-loop power optimization scheme is the crown jewel of the design flow, there is still far, far more to the development side of this kit. If you’re into model-based design, the kit supports initial waveform development in MATLAB/Simulink with design flows to both hardware and software components of the system. Hardware-level implementation on the FPGA side is handled by Xilinx’s System Generator and ISE toolset. Software implementation can be managed using The MathWorks Real-Time Workshop and TI’s Code Composer Studio.
In the software environment, Green Hills’s Integrity RTOS runs on the ARM9, topped with Objective Interface’s ORBExpress (Object Request Broker) middleware, making the system CORBA-enabled (Common Object Request Broker) for waveform portability. Communications Research Centre (CRC) of Canada supplies a Software Communications Architecture (SCA) core framework for the kit.
The plethora of press releases accompanying this announcement proclaim a six-month typical savings in design time for SDR development. Given the comprehensive nature of the kit, we’d guess that number would be easily achievable. Beyond the time savings, however, the kit should also significantly reduce the expertise barrier to SDR implementation – a substantial obstacle for many teams. If you’re wondering if it’s for you – we’d say spring for the $2900 eval kit. It’s hard to imagine a lower-risk easy entrée into the SDR domain.