Multi-madness is upon us these days. Multi-core, multi-thread, and multi-processor mania has made a mess of the previously well-ordered software tools and operating systems market, creating abundant opportunities for innovation. Single processor computing is at its heat limit, and the new way to get more cpu power focused on your problem is to pile on the processors and parallelize your application.

Much has been made in the technical press about various approaches for automatically parallelizing general-purpose computing. However, there are occasional outstanding opportunities to create domain-specific solutions that can elegantly and efficiently elevate the performance of mission-critical … Read More → "Parallelizing PCB"

Over the past few years, FPGAs have risen from a whisper to a roar at the Embedded Systems Conference. This year, at the newly re-relocated event (back in San Jose after a few-year foray up to San Francisco), there was barely a booth on the show floor without boards bearing FPGAs connected to cameras, displays, LEDs, remote-control cars, bins of bouncing balls, Dance Dance Revolution sensor pads, and even to the inner-workings of our old, remarkably destructive friend Cyclonebot’s 220-pound, half-inch-plate-titanium-clad frame.

Originally, … Read More → "Undertow of Ubiquity"

FPGAs are making big inroads in the embedded systems space as system-on-chip platforms. The recipe is solid – whip together a processor with some peripherals all connected to an on-chip bus or switch fabric. Add a little off-chip RAM and Presto – instant embedded system, ready to be changed at a moment’s notice, even after it’s in your customers’ hands. From 50,000 feet, it looks like the ideal solution for leading-edge embedded development. Of course, like any seemingly idealized solution, it has its … Read More → "C to FPGA"

Craig (not his real name) is the lead engineer on his company’s most important project. So far, Craig has been worth his weight in gold (which is about $1.6M assuming $550 per troy ounce at his current weight of 2916 troy ounces). Besides working out regularly to keep those unwanted troy ounces off, Craig keeps up with the very latest FPGA technologies so he can make solid decisions in creating his company’s new flagship electronic product.

This time, Craig chose a state-of-the-art 90nm FPGA as the centerpiece of his masterpiece. The product fit was perfect. Before this … Read More → "Go, Stop, Yield"

Achieving timing closure in today’s increasingly large and complex digital integrated circuit designs – irrespective of whether they are realized using FPGA, Structured ASIC, or even Standard Cell ASIC fabric – is becoming evermore problematic with the latest design targets running at aggressive clock speeds.

The majority of today’s designers typically code in RTL using Verilog or VHDL. Also, there is some use of C/C++/SystemC coupled with behavioral synthesis technology in certain application areas. Unfortunately, both of these approaches have specific, but different, disadvantages associated with them. As we shall see, … Read More → "Are You Designing with Too Many Significant Figures?"

I was at DATE 2006, a tradeshow in Germany. My cell phone started buzzing with calls, voicemails and e-mail. People were stopping me on the show floor – pulling me aside, whispering rapidfire questions – always small variations on a theme. “Did you hear that LSI Logic is killing RapidChip? Do you think that structured ASIC is dead? Are other structured ASIC vendors pulling out as well? Will FPGAs wipe out the structured and platform ASIC space entirely? What’s Altera doing? What about ChipX? Isn’t AMI doing structured as well? Has eASIC been acquired yet? What have … Read More → "Ask for Whom the Bell Tolls"