A couple weeks ago we looked at the state of FPGA low-power design from the standpoint of hardware. We saw a range of features, from very little to branded feature sets. But none of that matters without tools: tools are the window into the silicon, and no silicon feature has a shred of value unless a tool uses it (as can be testified to by the scores of now-defunct PLD businesses that were run by “the cheapest silicon always wins and software is annoying” types). And with a domain like low-power design, the tools can … Read More → "Making FPGAs Cool Again – Part 2"

The royalty walk quietly among the common folk here.  The thick-carpeted mahogany-veneered opulence typical of high-tech presidential palaces is nowhere to be seen.  Instead, on an ordinary floor in an ordinary building overlooking a nondescript cube farm are two adjacent rooms that would probably be conference rooms at your company.  Not the special, glossy, wood-wrapped, electric-view-screen-and-sound-system, “we entertain important clients in here” style of conference rooms, but rather the “grab your coffee and duck in here so we can scribble some stuff on the whiteboard” type.  In your company, each of these would probably be named after a river … Read More → "Passing the Torch"

There has been significant research to support the potential performance gains available through the use of reconfigurable hardware for certain classes of computationally-intensive tasks. However, despite well-known advantages, the technology has historically struggled to gain a strong foothold in the high-performance computing (HPC) marketplace. While there were many reasons for this lack of early widespread acceptance, one major issue has been a lack of standards surrounding reconfigurable processors and the absence of a standardized system architecture that can effectively employ them.

Many of the technological barriers to widespread use of reconfigurable computers have been overcome, and with … Read More → "Reconfigurable Computing for Acceleration in HPC"

It was a demonstration that buzzed around the (admittedly small incestuous) industry. A digital clock being powered by a grapefruit. It’s the kind of thing you might see on the Discovery Channel these days, but back in the day, Phillips/Signetics created a local stir with their comparatively ultra-low-power CPLDs. At that time, it was competing with the incumbent PALs that drew about 180 mA of current (and competing with their half- and quarter-power versions made possible by CMOS encroaching on an erstwhile bipolar domain). As the smaller devices became commoditized, the spotlight moved to FPGAs, … Read More → "Making FPGAs Cool Again – Part 1"