Today’s high-capacity and high-performance FPGA designs are becoming more complex and require more third-party intellectual property (IP) cores. These hard IP blocks include pecialized high-speed multi-gigabit transceiver (MGT) I/O cores, PCI Express cores, clock management modules, FIFOs and complex processor cores, such as the PPC440 in the Virtex5 device. The DSP clock management cores (DCMs), BlockRAMs, and FIFO models are in a class of Hard IP cores provided in standard libraries because the simulation models do not require source code protection. However, the other class of Hard IP cores, which includes MGT I/O cores, PCI … Read More → "Performance Improvements with New Secure IP and FAST Simulation Mode Models"

It used to be so simple. PLDs provided a medium by which you could create and modify logic without having to make any board changes. All the variability was on the inside; the outside consisted of I/Os, and, back in the day, that meant one thing: TTL. Eventually, when CMOS became more prevalent, the less-often-used rail-to-rail CMOS interface was available, but those I/Os were on different devices that were dedicated to the CMOS low-power market.

Well, the first hints that the age of innocence was coming to an end appeared with … Read More → "Employing an I/O Interlocutor"

There’s a new kid in class.

We’ve all been through this scenario before.  All the players are comfortable in their established roles.  The leader tries to stay ahead and always communicates with the purpose of maintaining the perception of leadership.  The second player vies constantly with the leader for supremacy and mind-share, always trying to one-up the alpha dog.  The third through fifth players are constantly flanking, trying to differentiate and establish themselves based on supremacy in a particular niche.

For years now, Xilinx, Altera, Lattice, Actel, … Read More → "New Kid in Class"

Introduction

Over two-fifths of FPGA design projects fall behind schedule. In order to reduce risk of delay of product delivery, changes need to be made not just in verification and production but also in the design process. Design simplification must be a principle that starts at the beginning of the project life cycle – before verification of complex code has become the bottleneck that delays project delivery.

For FPGA design, there are several methodologies that can be adopted to make life easier for both design and verification engineers. Two of these … Read More → "Avoid FPGA Project Delays by Adopting Advanced Design Methodologies"