As FPGAs increase in density, system designers are using these increased densities to the maximum by creating larger and more complex designs. These large designs are based on design requirements that either requires adding new functionality to an existing application such as a channel card or a line card used in wireless applications or reducing board real estate by combining the functionality of two chips into a single device or creating new designs for new applications.

These varied designs could contain … Read More → "How Physical Synthesis Enables FPGA Design Productivity"

The system is both elegant and enigmatic.

When visitors see the RocketDrive sitting on your lab bench (particularly if it is plugged into the handsome show-floor-worthy box currently making the rounds at trade shows), your “cool factor” will definitely creep up a notch or two. When you use it to help you knock bugs out of your next FPGA design, you’ll most likely be pleased with your purchase. GateRocket’s RocketDrive is a useful tool for FPGA designers.

You have to be careful, though, not to think about it too hard.

You … Read More → "GateRocket Blasts Off"

Introduction

Prototyping an ASIC, ASSP, or SoC onto a single FPGA is not without its challenges. You have to deal with differences in ASIC and FPGA architectures, optimize for performance and area requirements, and account for a debug strategy. Unfortunately, this is only the tip of the  iceberg when tasked with implementing an ASIC onto a multi-FPGA platform. Currently, the largest FPGAs have a capacity of roughly 1.5 M equivalent ASIC gates, so when prototyping a chip larger than this, a multi-FPGA strategy must be in place, and several more pitfalls must be accounted … Read More → "A Synthesis & Partitioning Strategy for Effective Multi-FPGA Prototyping"

Exponentials are exciting!

Anything in the real world that follows an exponential curve is a recipe for increased adrenalin production.  If we’re bopping along in our normal linear lives, and we bump into a geometric progression, we (those of us that took math, anyway) naturally expect that we’re in for a short and exciting ride.  Something that happens in twos or fours today will be exploding into the 128s and 256s by the end of the week, and next month will be flaming out in the bazillions.  Although these events can have … Read More → "FPGAs and the IC Bubble"

Over in one of our sister pubs, we did a review of some of the challenges of DDR last year. In particular, DDR3 has some incredible timing subtleties that have to be managed. DDR controllers are available as IP for FPGAs, but they still have to be connected to the memories on the board. And those board connections can seriously affect whether or not the timing requirements of the DDR protocols are properly met.

Mentor has just announced new versions of their HyperLynx PI and SI board power … Read More → "Simplifying DDR"