As FPGAs increase in density, system designers are using these increased densities to the maximum by creating larger and more complex designs. These large designs are based on design requirements that either requires adding new functionality to an existing application such as a channel card or a line card used in wireless applications or reducing board real estate by combining the functionality of two chips into a single device or creating new designs for new applications.
These varied designs could contain legacy code for an application or a DSP class design that has a high latency requirement. For such classes of designs the synthesis tools may not optimize the design optimally, which leads to long critical paths. The reason for these long critical paths is that logic synthesis tools depend on estimated delays to synthesize designs.
These long critical paths create a timing closure problem where there is performance degradation, thus forcing designers to rewrite RTL code to improve these long critical paths. Additionally there could be several iterations before the user gets optimal RTL code that meets timing specifications. This in turn adds additional schedule delays for the product to reach the market.
Another problem that manifests itself in designs with a high percentage of logic utilization is routing congestion. Designers must either recode the RTL or try different settings within the place and route tool to improve the performance on these critical paths. Such trial and error methods also lead to increased time-to-market and hampers productivity.
These two problems present a challenge to designers trying to close timing and thus make timing closure the primary problem faced by system designers. One solution that can resolve both problems and improve performance is a physical synthesis tool. Physical synthesis tools have been provided by FPGA vendors and third party EDA tool vendors for some time. The primary function of a physical synthesis tool is to improve timing closure (i.e. performance) by reducing the number of critical paths with the fewest number of iterations and in turn reduce time to market.
The design flow for a physical synthesis tool is shown in Figure 1 works in the following manner. Logic synthesis tools use algorithms such as logic replication that replicates high-fanout logic or retime registers in long logic paths for improved performance. The physical synthesis tool differs from logic synthesis tools by using accurate delays and accurate information to optimize the critical paths using similar algorithms. Logic synthesis tools relay more on global delay estimates, while physical synthesis tools use more accurate delays.
Figure 1. A Possible Design Flow Illustrating How a Physical Synthesis Tool Works
Figure 1 shows that a physical synthesis tool is also run as part of the whole synthesis flow. Physical synthesis tools are run as part of synthesis tools, but after logic synthesis, for additional clarity it can be referred to early physical synthesis. In this flow after logic synthesis the tool models placement and routing of the whole design and tries to improve the critical paths again by using well known algorithms like retiming and replication. Some EDA vendors have launched such tools based on this level of accuracy to elevate the timing closure problems.
Where does physical synthesis derive its accurate information?
Figure 1 shows another physical synthesis tool flow that is first invoked after the placement stage in a typical flow. At this stage the design is fully placed and by using delay estimates for interconnect delay, the critical paths can be more accurately predicted. By using the algorithms described above, the critical paths can be improved to meet performance requirements. All this manipulation is done without changing a single line of RTL code. It is possible that retiming a register in a synthesis tool with inaccurate delays could hinder performance; while having the design placed allows the physical tool to make intelligent decisions that help predict which registers to retime and improve performance.
Today’s FPGA architectures have two levels or hierarchies. The first level is called logic blocks that is a group or collection of individual logic cells called labs. The second level of hierarchy consist of logic cells, where each logic cell contains a pair of registers, a pair of look-up tables, and a pair of full-adders. In Altera FPGAs such logic cells are called adaptive logic modules (ALMs). These logic blocks when stacked in an array and connected with a number of wires (routing wires) along with on-chip memory blocks, DSP blocks and IO Blocks create the architecture of an FPGA.
In a typical design flow the placement is done twice. The first step is to place the entire design on the logic block level. Once this is done, the placement algorithm places the logic at the logic cell level. It is very intuitive to see that physical synthesis results will improve, after the second round of placement is invoked as the physical synthesis tool relies on the accurate information that is available and will yield much better quality of results (QoR), which will improve productivity.
Another application where a physical synthesis tool can help improve productivity is in conjunction with Incremental Design Flow. In this methodology rather than having physical synthesis enabled for the whole design it can be applied on a per module basis. This helps not only reduce compile time, but improves performance as the physical synthesis tool focuses on the module where it is required.
A physical synthesis tool is part of Altera’s Quartus II place and route tool. This physical synthesis tool offers the users the choice of optimizations and effort levels to improve performance and productivity. Following is a list of some of these optimization choices that can be controlled by the user:
Physical Synthesis for Performance
– Physical synthesis on combinational logic: the tool further optimizes combinational logic based on accurate information
– This option allows Quartus II physical synthesis tool to resynthesize the combinational logic in a design to reduce delay along the critical path and improve performance
– Physical synthesis on asynchronous pipelining: pipeline asynchronous signals such as loads and clears
– This option allows the Quartus II physical synthesis tool to insert pipelining registers on loads and clear signals to improve performance
Physical Synthesis for Registers
– Retiming: allows the tool to automatically perform register balancing
– This option allows Quartus II to move registers across combinational circuits to improve performance
– Register Replication: replicates registers with high fan-out outputs
– This option allows Quartus II to replicate registers based on placement information to improve performance
Physical Synthesis for Fitting
– Physical synthesis on combinational logic: this is a second round of optimizations on combinational circuits
– Quartus II performs second round of optimization on combinatorial circuits to help fit the design
– Perform logic to memory mapping: this maps combinational logic to memory to save area
– Quartus II automatically maps combinational logic into unused memory blocks to reduce area and fit the design
Quartus II also offers an Incremental Design Flow that supports both top-down as well as bottom-up flows. Such a flow is used to reduce compile time and improve performance.
Figure 2. Physical Synthesis Tool Settings Shown in Quartus II Design Software
Today most companies are vying to reach the market first with their products. As a strategic initiative, productivity and time to market are key parameters to the success of any product. Utilizing a physical synthesis tool improves performance of the design, translates to shorter design cycles, and improves productivity. Using such a tool efficiently will prove to be a clear winner in the hands of the designers.
About the Author: Ajay Jagtiani is a technical marketing manager at Altera Corporation. His focus is on the timing closure, synthesis and formal verification interfaces for Altera’s Quartus® II design software. Mr. Jagtiani has eight years of experience in the design automation and semiconductor industry. Prior to joining Altera, Mr. Jagtiani was the Senior Customer Support Manager at Atrenta, Inc. with responsibility for its verification product. Mr. Jagtiani has held management and application engineering positions at Synplicity and Lattice Semiconductor. He holds a BSEE from the University of Bombay, an MSEE from the Stevens Institute of Technology in Hoboken, NJ and is currently pursuing an MBA at Santa Clara State University.
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