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WD® Launches Newest WD VelociRaptor® – The World’s Fastest SATA Hard Drive Now Has Twice the Capacity

LAKE FOREST, Calif., April 6 /PRNewswire-FirstCall/ — WD® (NYSE: WDC) announced today that it is now shipping WD VelociRaptor® 450 GB and 600 GB hard drives, the next generation of its 10,000 RPM SATA family of hard drives. The new WD VelociRaptor hard drive is designed for blade servers, high-performance PCs, Mac® computers, professional workstations, as well as 1U and 2U rack servers that require a balance of high performance and … Read More → "WD® Launches Newest WD VelociRaptor® – The World’s Fastest SATA Hard Drive Now Has Twice the Capacity"

Zarlink’s New ClockCenter Platform Powers Growth for Timing Portfolio

  • ClockCenter “any rate, any port, all the time” platform brings Zarlink’s Network Timing expertise to new markets, including high-speed optical transport networks (OTN)
  • Ciena Corporation deploys ClockCenter products in switching systems that enable multiple communication services over OTN

    OTTAWA, CANADA, April 6, 2010  Zarlink Semiconductor (TSX: ZL) today introduced ClockCenter, the industry’s first “any rate, any port, all the time” platform for high-speed optical transport network (OTN) and communications equipment. … Read More → "Zarlink’s New ClockCenter Platform Powers Growth for Timing Portfolio"

    TSMC Delivers Interoperable EDA Formats for Advanced Process Technologies

    HSINCHU, Taiwan, R.O.C., April 6 /PRNewswire-FirstCall/ — Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) has made available several unified and interoperable electronic design automation (EDA) technology files for its 65 nanometer (nm), 40nm and 28nm process nodes. The design technology file suite includes interoperable process design kit (iPDK), interoperable design rule check (iDRC), layout-versus-schematic (iLVS), and interoperable interconnect extraction (iRCX).

    The iPDK, iDRC, iLVS, and iRCX technologies are developed and jointly validated with TSMC’s EDA partners under the industry-wide Interoperability Project that is an integral part of the company’s Open Innovation Platform™ (OIP).</ … Read More → "TSMC Delivers Interoperable EDA Formats for Advanced Process Technologies"

    Coming to a Rave Near You

    We keep remaking the world in ways that nature never could. Or, at least, never did. It started innocently enough centuries ago with humans creating structures that didn’t exist in nature. Then we created materials that don’t occur in nature. We’ve even created elements – lots of them, anything bigger than uranium – that don’t exist in nature. Or at least if they do, we haven’t found them there.

    It’s all a process of observing what exists in nature, figuring out how those … Read More → "Coming to a Rave Near You"

    Have You Really Verified Your Multi-rail, Low Power Design?

    Until recently, low power designs used a single voltage supply and a host of voltage control techniques such as power domains, power shutdown or power gating, and standby to reduce power consumption. However, process geometries are shrinking rapidly and power is not scaling well, posing a barrier to Moore’s law. Consequently, low power designers have adopted increasingly aggressive techniques such as using multiple supply voltages. Multiple supply voltages imply a design with blocks and cells featuring multiple supply rails, further compounding the already daunting task of verifying low power designs. Incomplete or improper verification of such designs leaves … Read More → "Have You Really Verified Your Multi-rail, Low Power Design?"

    Lattice Announces Updates And Enhancements To Its FPGA Design Tool Suite

    HILLSBORO, OR — APRIL 5, 2010 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 1 for Version 8.0 of its ispLEVER® FPGA design tool suite.  Service Pack 1 is an important update for users of LatticeECP3™ FPGA devices. “Service Pack 1 enhances and extends design support of the LatticeECP3 family to enable users to achieve low cost, low power design goals.  More specifically, this important update allows users of the ECP3-150EA device to design with even greater confidence that the board-level behavior of their design, such as power and timing, will match what … Read More → "Lattice Announces Updates And Enhancements To Its FPGA Design Tool Suite"

    Texas Instruments WiLink™ 6.0 solution now available on the OMAP35x Evaluation Module

    DALLAS (March 16, 2010) – Giving designers working on the OMAP35x platform the opportunity to incorporate wireless connectivity technology into their portable designs, Texas Instruments Incorporated (TI) (NYSE: TXN), today introduced the availability of its WiLink™ 6.0 (WL1271) solution on the OMAP35x processor Evaluation Module (EVM).  With this solution, TI is making wireless connectivity solutions available for design in a broad array of applications. One of the industry’s smallest solutions to integrate wireless LAN (WLAN) and Bluetooth® technologies in a single chip, the WL1271 solution sparks futuristic designs on the … Read More → "Texas Instruments WiLink™ 6.0 solution now available on the OMAP35x Evaluation Module"

    Cypress Introduces Easy-to-Use Development Platform for iPhone and iPod Accessories Based on Revolutionary PSoC® 3 Architecture

    SAN JOSE, Calif., April 5, 2010 – Cypress Semiconductor Corp. (Nasdaq: CY) today introduced a new development platform for Apple iPhone and iPod accessories based on its new PSoC® 3 architecture. Designers can use Cypress’s new CY8CKIT-023 PSoC Expansion Board Kit For iPhone & iPod Accessories – a plug-in board to Cypress’s CY8CKIT-001 PSoC … Read More → "Cypress Introduces Easy-to-Use Development Platform for iPhone and iPod Accessories Based on Revolutionary PSoC® 3 Architecture"

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