In music, Legato means smooth and connected, without distinct breaks. Or, in electronics parlance – analog. Analog circuits are arguably the most difficult to design and the most complex to simulate. Engineers with mystical knowledge and decades of experience toil endlessly to find just the right combination of component values that will yield the desired results. And that’s just for the nominal case.
Now, try putting that analog device you just designed into mass production with process and temperature variations, power supply inconsistencies, and any of the myriad possible combinations of mayhem that the universe inflicts on real-world systems, and you’ve got a problem that can be practically unmanageable. How do you simulate with enough variations to know that you’ve caught the failure modes customers may see in the field? How do you estimate longevity when systems are targeted for extended-life applications? How do you know what you don’t know?
Cadence Design Systems released the new Legato Reliability Solution this month, with the aim of reaching beyond the design cycle to the entire product life cycle for analog devices targeting the automotive, medical, industrial, aerospace, and defense application areas. Cadence claims Legato Reliability is the first “complete” analog design-for-reliability solution, and it represents a bit of a departure from the usual design-centric focus that has been the company’s wheelhouse for decades.
With systems like automobiles continually growing in the amount of electronic content, and with the role of that electronic content becoming increasingly mission- and safety-critical, making sure that the electronic components of a system have at least the lifespan of the mechanical components becomes a key issue. And, because of the harsh realities of mass production, we want to have test procedures that catch bad components before they are integrated into complex systems. And, we need to design and verify with real-world operating conditions and process variations taken into account, and to consider the stresses that will be thrown at field-deployed devices to be sure that failure does not occur before wear-out.
For many of these applications, the useful life needs to be fifteen years or greater, and assuring that kind of longevity requires more than the old-fashioned “over design it a bit” mentality. Cadence’s solution is based on the company’s Virtuoso custom IC design platform and the Spectre accelerated parallel simulator.
The first stop in our quest for quality is to reduce field failures by doing defect analysis. Defect-oriented testing can help eliminate dice with manufacturing defects and resulting test escapes. Cadence includes defects in simulation of analog test programs in order to estimate the test coverage of defective parts. Normally, this is a very compute-intensive process, and Cadence claims to have accelerated the defect simulation by up to 100x compared with conventional methods. The result is improved tests that can more efficiently test parts yielding higher coverage and fewer test escapes.
The process of defect simulation begins with identifying the potential manufacturing faults and then collapsing the redundant ones. Cadence’s Virtuoso AMS Designer then performs analog fault simulation that compares the results from each defective circuit with the results from a “good” circuit to see which defects would be caught by the test suite. The results are used to calculate test coverage using the Virtuoso ADE suite.
When components are deployed in the field, thermal stress is the primary mechanism for aging and premature failure of them. In applications such as automotive, high-power dissipation in a high-temperature environment can result in thermal overstress. Electro-thermal analysis can be applied to dynamically simulate temperature rise and validate temperature protection circuits. Cadence’s electro-thermal simulation starts by extracting a thermal model of the die from design data. Then, during electrical simulation, the instance temperature is updated at each time step, accounting for both self-heating and heat transfer from adjacent devices.
Advanced-aging analysis is a technique that evaluates the factors that affect and accelerate device wear-out (such as temperature and process variation) and uses that data to accurately predict device wear-out. Since FinFET transistors wear differently than traditional planar transistors, the tool incorporates a special aging model for device degradation of devices fabricated on advanced nodes with FinFET transistors. Using this technique, design teams can design for the product lifetimes required for their application without extreme or unbalanced over-design.
Advanced aging analysis takes in the netlist and circuit information, reliability models, and a mission profile that includes expected operating conditions such as temperature, duty cycle or on/off time, and burn-in. The tool applies aging analysis and self-heating analysis to those models and that data and does a monte carlo simulation to predict statistical lifetime and wear-out.
The combination of these techniques is critical in application areas such as automotive, where premature failures can result in loss of life, field diagnosis is expensive and time consuming, and operating conditions can be brutal over the entire fifteen-year expected life of electronic components. It turns out that 80% to 95% of field failures are due to the analog or mixed-signal portion of products, and most field failures of power components in automobiles are caused by solder and bondwire fatigue due to thermal overstress. That means that these techniques could go a long way toward reducing the failure rate to the automotive industry’s target defect rate of 0 defective parts per million (dppm).
Cadence’s expansion into this area of test and reliability is a natural extension of the company’s existing infrastructure for design and analysis, and it allows engineers to think and design more critically past the “first shipment” milestone. Taking the entire product life cycle into account during the initial design phase should have a profound impact on the reliability and safety of systems using analog parts, and Cadence’s smooth integration of those capabilities into their existing workflows and data models should simplify adoption for design teams. It will be interesting to watch the adoption of this methodology and technology, and to see how well EDA companies are able to comprehend and address the challenges of system design that extend far beyond the usual design cycle.
