Microchip’s FPGA offering has a heritage of low power and high reliability. Beginning with Actel’s antifuse- and flash-based devices that were picked up and advanced by Microsemi and then later joined Microchip’s formidable stable in a subsequent acquisition, the fundamental approach hasn’t changed – building the lowest-power mid-range FPGAs on the market.
Now, that agenda has advanced even further with the announcement of new devices that target edge computing and interface applications across a wide range of end markets. While Actel and Microsemi focused primarily on aerospace, defense, and other niches, Microchip has brought the venerable PolarFire and PolarFire SoC FPGA families to a much broader audience.
And, before we jump into the details of the new FPGAs and FPGA SoCs, it may be prudent to review what we mean by “mid-range FPGA” and “edge” in this context. These two terms are used and abused to describe a wide and disparate range of technologies. Lattice’s “mid-range” ECP3 tops out at around 150K LUTs, but Xilinx’s “mid-range” Kintex family and Microchip’s PolarFire FPGA families both go up to ~500K LUTs. Lattice’s “mid-range” ECP3 tops out at around 150K. This distinction is important today, because Microchip’s announcement is actually about two new devices on the small end of the “mid-range,” extending the family down to about 50K LUTs, but with all the grown-up interfaces and features we’d associate with much larger devices.
Regarding “edge” – we hear this term applied to everything from the servers that may be managing hundreds of security cameras inside a big-box store to body-worn IoT devices powered by harvested energy. Obviously, that’s quite a range. In this case, we are talking about applications that sit near the center of that “edge” domain. Think handheld and portable equipment, 5G infrastructure, security cameras, automotive ADAS…
So, why is announcing new, smaller FPGAs for an existing family interesting?
Power. And the edge. When we are trying to fit within a narrow power budget, any LUTs on our FPGA that aren’t being used are just sitting there leaking current. Not cool. And, speaking of “not cool,” if we can keep our FPGA – and our board in general – cool enough, we can do away with those pesky, power-sucking fans and heavy heat sinks. That’s a win on all fronts. Less power used by the FPGA, zero power used by the fan that is no longer required to cool the FPGA, and less BOM cost, footprint, and weight for the extra components that aren’t required. On top of those benefits is the less obvious higher reliability – lower FIT numbers we get when our device – and our whole system – consistently operate at lower temperatures.
We might even be able to get by with a smaller power supply or smaller batteries. Low power is a gift that just keeps on giving in a virtuous cycle.
But often, in the FPGA world, going for a smaller device also means giving up high-speed interfaces and IO that we might need, and other features that might be critical to our design. That’s what’s cool about these new devices from Microchip, they strip down the power without stripping down the functionality.
The new MPF050 extends the PolarFire FPGA family down to 50K LUTs, but it still boasts 12.7 Gbps SerDes transceivers and the ability to process UHD video and 10G edge data path infrastructure. The new MPFS025T extends the PolarFire FPGA SoC family down to 25K LUTs, while maintaining the full-featured quad core RISC-V microprocessor subsystem, flexible 2MB L2 cache, defense-grade security, and LPDDR4 memory support. This combination of low power, along with extended features and performance, puts these devices in a class by themselves in the FPGA space.
Diving into the details, the new MPF050 PolarFire FPGA has 48K logic elements (LUT4 +DFF), 150 DSP blocks with 18×18 MACCs, 3.6 Mbits total on-chip RAM, 216Kbits uPROM, 4 lanes of 12.7 Gbps SerDes, 2 PCIE GEN2 endpoints/root pors, and 176 total user IO. The new MPFS025T PolarFire SoC FPGA – which includes a four-core RISC-V processing system – has 23K logic elements, 68 DSP blocks with 18×18 MACCs, 1.8 Mbits total on-chip RAM, 194 Kbits uPROM, 4 lanes of 12.5 Gbps SerDes, 2 PCIe GEN2 endpoints/root ports, and 108 total FPGA IO and 136 total MSS IO. Both devices can fit in a tiny 11x11mm package, or in a 19x19mm package, depending on your IO needs. Both devices are expected to deliver in Q1 2022.
Microchip claims that the new FPGA consumes about half the power of competitive FPGA devices (on comparable tasks), and the SoC consumes 45% less power than competitive devices while generating better performance. That kind of power savings can generate the kind of knock-on benefits we discussed earlier and can be a true enabler for many types of applications.
It is interesting that the market for these mid-range and low-end FPGAs – such as those sold by Microchip, Lattice, and QuickLogic – seems to be growing at a brisk pace, yet is largely ignored by the two largest FPGA companies. With Xilinx on track to be acquired by AMD, and Intel years into their acquisition of Altera, the high-end and data center focus of the two big suppliers is understandable, but it also leaves an exciting and lucrative market and application space that companies like Microchip are aggressively exploiting.
Microchip’s full-tilt embracing of RISC-V brings another interesting element to the story. By offering FPGA SoCs with powerful multi-core RISC-V subsystems, the company puts themselves in a unique spot in the market. As the RISC-V wave continues to build momentum, the ecosystem grows, and the universe of enthusiastic developers expands, Microchip’s FPGA SoC offering becomes more and more attractive.
It will be interesting to watch this mid-range battle evolve, as the market for these devices is certain to expand rapidly. Today’s push toward more compute acceleration at the edge, and the growing number of applications that require the computational power efficiency these devices offer – particularly for tasks such as edge AI inference – means a lot of teams will turn toward this type of mid-range FPGA.